dsp56858 Freescale Semiconductor, Inc, dsp56858 Datasheet - Page 30

• Manufacturer Part Number: dsp56858
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

4.6 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices.
sample timing and parameters that are detailed in
The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user
controlled wait states. The equation:
30
should be used to determine the actual time of each parameter. The terms in the above equation are defined as:
Operating Conditions: V
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
t
D fixed portion of the delay, due to on-chip path delays.
P
External
Note: The midpoint is V
The PLL is optimized for 4MHz input crystal.
Clock
parameter delay time
the period of the system clock, which determines the execution rate of the part (i.e. when the device is
operating at 120 MHz, P = 8.33 ns).
t = D + P * (M + W)
Characteristic
SS
10%
50%
90%
= V
2
SSIO
t
PW
IL
= V
+ (V
SSA
Figure 4-9 External Clock Timing
IH
= 0 V, V
– V
IL
DD
)/2.
Table 4-6 PLL Timing
56858 Technical Data, Rev. 6
= 1.62-1.98V, V
t
PW
1
Table
Symbol
DDIO
4-7.
f
t
f
osc
plls
clk
= V
DDA
= 3.0–3.6V, T
Min
40
—
2
t
fall
A
= –40° to +120°C, C
Typ
—
4
1
t
Max
Freescale Semiconductor
rise
240
L
10
4
≤ 50pF, f
Figure 4-10
10%
50%
90%
op
= 120MHz
V
V
Unit
MHz
MHz
IH
IL
ms
shows