dsp56858 Freescale Semiconductor, Inc, dsp56858 Datasheet
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... Data Sheet Technical Data 56800E 16-bit Digital Signal Controllers DSP56858 Rev. 6 01/2007 freescale.com ...
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... DSP56858 General Description • 120 MIPS at 120MHz • 40K x 16-bit Program SRAM • 24K x 16-bit Data SRAM • 16-bit Boot ROM • Access words of program memory or 8M data memory • Chip Select Logic for glue-less interface to ROM and SRAM • ...
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Part 1 Overview 1.1 56858 Features 1.1.1 Digital Signal Processing Core • Efficient 16-bit engine with dual Harvard architecture • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • • Four ...
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Six (6) independent channels of DMA • 8-bit Parallel Host Interface* • Time-of-Day (TOD) • GPIO * Each peripheral I/O can be used alternately as a GPIO if not needed 1.1.4 Energy Information • Fabricated in ...
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... Description Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted 56858 Technical Data, Rev. 6 Order Number 56800ERM DSP5685xUM DSP56858 DSP56858E 1 Voltage ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56858 are organized into functional groups, as shown in as illustrated in Figure 2-1. In Table 3-1 present. Table 2-1 56858 Functional Group Pin Allocations Power (V ...
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Logic Power I/O Power Analog 1 Power Address Bus Chip CS0 - CS3 (GPIOA0 - A3) Select HD0 - HD7 (GPIOB0 - B7) HA0 - HA2 (GPIOB8 - B10) HRWB (HRD) (GPIOB11) Host HDS (HWR) (GPIOB12) Interface HCS (GPIOB13) HREQ ...
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Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be disabled under software ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No DDIO DDIO DDIO DDIO V M11 61 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No F10 96 D4 F11 97 D5 E10 98 D6 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. HD0 J3 33 GPIOB0 HD1 K2 34 GPIOB1 HD2 L2 35 GPIOB2 HD3 J4 40 GPIOB3 HD4 L4 41 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. HD6 K5 43 GPIOB6 HD7 H5 44 GPIOB7 HA0 G10 90 GPIOB8 HA1 G11 91 GPIOB9 HA2 G9 92 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. C8 116 HDS HWR GPIOB12 D8 117 HCS GPIOB13 B8 118 HREQ HTRQ GPIOB14 Freescale Semiconductor Type Input Host ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. C7 119 HACK HRRQ GPIOB15 TIO0 B9 114 GPIOG0 TIO1 C9 112 GPIOG1 TIO2 D9 111 GPIOG2 TIO3 B10 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. MODE GPIOH1 MODE GPIOH2 K4 39 RESET K3 38 RSTO RXD0 L10 73 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. STD0 B6 131 GPIOC0 SRD0 C6 132 GPIOC1 SCK0 C5 133 GPIOC2 SC00 D6 134 GPIOC3 SC01 B5 135 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. STD1 E8 99 GPIOD0 SRD1 E11 100 GPIOD1 SCK1 E9 101 GPIOD2 SC10 D10 102 GPIOD3 SC11 D11 103 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. MISO B2 1 GPIOF0 MOSI C3 2 GPIOF1 SCK C2 3 GPIOF2 GPIOF3 XTAL H2 27 ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No. TCK L8 60 TDI K7 58 TDO G6 57 TMS TRST Freescale Semiconductor Type Input ...
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Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal BGA LQFP Name Pin No. Pin No Part 4 Specifications 4.1 General Characteristics The 56858 is fabricated in high-density CMOS with 5-volt tolerant ...
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This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation ...
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Table 4-2 Recommended Operating Conditions (Continued) Characteristic Frequency of external clock Frequency of oscillator Frequency of clock via XTAL Frequency of clock via EXTAL 1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must ...
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Table 4-4 DC Electrical Characteristics (Continued) Operating Conditions SSIO SSA Characteristic Input current low (pullups disabled) Input current high (pullups disabled) Output tri-state current low Output tri-state current high Output High Voltage Output Low ...
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Figure 4-1 Maximum Run I 4.3 Supply Voltage Sequencing and Separation Cautions Figure 4-2 shows two situations to avoid in sequencing the V 3.3V 1. Note rising before V , ...
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V should not be allowed to rise early (1). This is usually avoided by running the regulator for the V DD supply (1.8V) from the voltage generated by the 3.3V V rising faster than V . DDIO V should not ...
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Figure 4-5 shows the definitions of the following signal states: • Active state, when a bus or signal is driven, and enters a low impedance state • Tri-stated, when a bus or signal is placed in a high impedance state ...
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High Speed External Clock Source (> 4MHz) The recommended method of connecting an external clock is given in source is connected to XTAL and the EXTAL pin is held at ground, V bit in CGM must be set to ...
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External 90% 50% Clock 10 Note: The midpoint Operating Conditions SSIO SSA Characteristic External reference crystal frequency for the PLL PLL output frequency 2 PLL stabilization time ...
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M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible clock duty cycle derating. W the sum of the applicable wait state controls. See the “Wait State Controls” column of the ...
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Table 4-7 External Memory Interface Timing Operating Conditions SSIO SSA Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Data Out Valid to WR Asserted Valid Data Out Hold Time after ...
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Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Operating Conditions SSIO SSA Characteristic RESET Assertion to Address, Data and Control Signals High Impedance ...
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Normal stop mode power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and ...
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IRQA, IRQB A0–Axx, CS, RD, WR Figure 4-14 Interrupt from Wait State Timing t IW IRQA A0–Axx, CS, RD, WR Figure 4-15 Recovery from Stop State Using Asynchronous Interrupt Timing RESET Freescale Semiconductor t IRI RSTO Figure ...
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Host Interface Port Table 4-9 Host Interface Port Timing Operating Conditions SSIO SSA Characteristic Access time Disable time Time to disassert Lead time Access time Disable time Disable time Setup time Hold time ...
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HACK HD HREQ Figure 4-17 Controller-to-Host DMA Read Mode HA HCS HDS HRW HD Figure 4-18 Single Strobe Read Mode Freescale Semiconductor TACKDZ TACKDV TACKREQL TREQACKL TACKREQH TRADV 56858 Technical Data, Rev. 6 Host Interface Port TRADX TRADZ 37 ...
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HA HCS HWR HRD HD HACK HD HREQ Figure 4-20 Host-to-Controller DMA Write Mode 38 TRADV Figure 4-19 Dual Strobe Read Mode TDACKS TREQACKL TACKREQH 56858 Technical Data, Rev. 6 TRADX TRADZ TACKDH TACKREQL Freescale Semiconductor ...
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HA HCS HDS HRW HD Figure 4-21 Single Strobe Write Mode HA HCS HWR HRD HD Freescale Semiconductor TWDS TADSS TADSS TWDS TADSS TADSS Figure 4-22 Dual Strobe Write Mode 56858 Technical Data, Rev. 6 Host Interface Port TDSAH TDSAH ...
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Serial Peripheral Interface (SPI) Timing Operating Conditions SSIO SSA Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) low ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 4-24 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref) t ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 4-26 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...
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Quad Timer Timing Operating Conditions SSIO SSA Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. In the formulas listed clock cycle. For f ...
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Table 4-11 ESSI Master Mode Operating Conditions SSIO SSA Parameter Delay from SCK high to SC2 (wl) high - Master Delay from SC0 high to SC1 (bl) high - Master Delay from SC0 high ...
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SCKH SCK output SC2 (bl) output t TFSWHM SC2 (wl) output t TXVM t STD SC0 output t RFSBHM SC1 (bl) output t RFSWHM SC1 (wl) output t SM SRD Figure 4-29 Master Mode Timing Diagram Table 4-12 ESSI ...
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Table 4-12 ESSI Slave Mode Operating Conditions SSIO SSA Parameter Delay from SCK high to SC2 (bl) high - Slave Delay from SCK high to SC2 (wl) high - Slave Delay from SC0 high ...
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SCKH SCK input t TFSBHS SC2 (bl) input t TFSWHS SC2 (wl) input t FTXES t TXVS t TXES STD SC0 input t RFSBHS SC1 (bl) input t RFSWHS SC1 (wl) input t SS SRD Figure 4-30 Slave ...
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Serial Communication Interface (SCI) Timing Operating Conditions SSIO SSA Characteristic 1 Baud Rate 2 RXD Pulse Width 3 TXD Pulse Width the frequency of operation of the system clock in ...
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JTAG Timing Operating Conditions SSIO SSA Characteristic 2 TCK frequency of operation TCK cycle time TCK clock pulse width TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO ...
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TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) Figure 4-34 Test Access Port Timing Diagram TRST (Input Figure 4-36 Enhanced OnCE—Debug Event Input Data Valid TRST Figure 4-35 ...
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GPIO Timing Operating Conditions SSIO SSA Characteristic GPIO input period GPIO input high/low period GPIO output period GPIO output high/low period 1. In the formulas listed clock cycle. For f 2. ...
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Part 5 Packaging 5.1 Package and Pin-Out Information 56853 This section contains package and pin-out information for the 144-pin LQFP configuration of the 56858. Orientation Mark MISO MOSI PIN 1 SCK SS V DDIO V DDIO ...
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Table 5-1 56858 Pin Identification by Pin Number Pin Pin Signal Name No. No. 1 MISO 37 2 MOSI 38 3 SCK DDIO DDIO SSIO 8 RD ...
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Table 5-1 56858 Pin Identification by Pin Number (Continued) Pin Pin Signal Name No. No DDA SSA SSA 27 XTAL 63 28 EXTAL ...
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Figure 5-2 144-pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. Freescale Semiconductor 56858 Technical Data, Rev. 6 Package and Pin-Out Information 56853 55 ...
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This section contains package and pin-out information for the 144-pin MAPBGA configuration of the 56858 DDIO SSIO DD V RXD1 TIO3 TIO0 SSIO V SC12 TXD1 TIO1 DDIO V SC11 SC10 ...
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Table 5-2 56858 Pin Identification by Pin Number Pin No. Signal Name Pin No A10 K6 A11 J8 A12 ...
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Table 5-2 56858 Pin Identification by Pin Number (Continued) Pin No. Signal Name Pin No. H11 CS2 H10 CS3 F10 D3 F11 D4 E10 ...
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D X LASER MARK FOR PIN 1 Y IDENTIFICATION IN THIS AREA E 0.20 e 11X 11X 144X VIEW M-M 0. 0.10 Z Figure 5-4 144-pin MAPBGA Mechanical ...
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Part 6 Design Considerations 6.1 Thermal Design Considerations An estimation of the chip junction temperature, T Equation Where ambient temperature ° package junction-to-ambient thermal resistance °C/W θJA ...
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As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection ...
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All inputs must be terminated (i.e., not allowed to float) using CMOS levels. • Take special care to minimize noise levels on the V • When using Wired-OR mode on the SPI or the IRQx pins, the user must ...
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... MAP Ball Grid Array (MAPBGA) DSP56858 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) *This package is RoHS compliant. Freescale Semiconductor Pin Package Type Count 144 144 144 56858 Technical Data, Rev. 6 Electrical Design Considerations Frequency Order Number (MHz) 120 DSP56858FV120 120 DSP56858VF120 120 DSP56858FVE * 63 ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56858 Rev. 6 01/2007 ...