dsp56858 Freescale Semiconductor, Inc, dsp56858 Datasheet - Page 21

• Manufacturer Part Number: dsp56858
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Signal
Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Name
TRST
TDO
TMS
TCK
TDI
Pin No.
BGA
G6
L8
K7
L7
J7
Pin No.
LQFP
60
58
57
59
56
Output(Z)
Type
Input
Input
Input
Input
56858 Technical Data, Rev. 6
Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
Test Data Input (TDI)—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Test Data Output (TDO)—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in
the Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
Test Mode Select Input (TMS)—This input pin is used to sequence
the JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Note:
Test Reset (TRST)—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The
only exception occurs in a debugging environment, since the
Enhanced OnCE/JTAG module is under the control of the debugger. In
this case it is not necessary to assert TRST when asserting RESET.
Outside of a debugging environment RESET should be permanently
asserted by grounding the signal, thus disabling the Enhanced
OnCE/JTAG module on the device.
Note:
to be used in a debugging environment, TRST may be tied to V
1K resistor.
Always tie the TMS pin to V
For normal operation, connect TRST directly to V
Description
DD
through a 2.2K resistor.
SS
. If the design is
SS
through a
Introduction
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