epm9560wc208-20c Altera Corporation, epm9560wc208-20c Datasheet - Page 3

• Manufacturer Part Number: epm9560wc208-20c
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
General
Description
Note:
(1)
Table 4. MAX 9000 Performance
16-bit loadable counter
16-bit up/down counter
16-bit prescaled counter
16-bit address decode
16-to-1 multiplexer
Internal logic array block (LAB) performance is shown. Numbers in parentheses show external delays from row
input pin to row I/O pin.
Application
The MAX 9000 family of in-system-programmable, high-density, high-
performance EPLDs is based on Altera’s third-generation MAX
architecture. Fabricated on an advanced CMOS technology, the EEPROM-
based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin
delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed
grade of the MAX 9000 family is compliant with the PCI Local Bus
Specification, Revision 2.2.
MAX 9000 devices.
Table 4
The MAX 9000 architecture supports high-density integration of system-
level logic functions. It easily integrates multiple programmable logic
devices ranging from PALs, GALs, and 22V10s to field-programmable
gate array (FPGA) devices and EPLDs.
Table 3. MAX 9000 Speed Grade Availability
Macrocells Used
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
shows the performance of MAX 9000 devices for typical functions.
Device
Note (1)
16
16
16
1
1
MAX 9000 Programmable Logic Device Family Data Sheet
7.7 (12.1)
5.6 (10)
144
144
144
-10
Table 3
-10
v
v
shows the speed grades available for
Speed Grade
10.9 (18)
7.9 (15)
118
118
118
-15
Speed Grade
v
v
v
v
-15
10 (20)
16 (26)
100
100
100
-20
-20
v
v
v
v
Units
MHz
MHz
MHz
ns
ns
3