epm2210gm100i Altera Corporation, epm2210gm100i Datasheet - Page 83

• Manufacturer Part Number: epm2210gm100i
• Description: Section I. Max Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
July 2008
t
t
t
t
t
t
t
t
t
Symbol
LUT
COMB
CLR
PRE
SU
H
CO
CLKHL
C
Table 5–15. LE Internal Timing Microparameters
LE combinational LUT
delay
Combinational path
delay
LE register clear delay
LE register preset
delay
LE register setup time
before clock
LE register hold time
after clock
LE register clock-to-
output delay
Minimum clock high or
low time
Register control delay
Parameter
f
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density.
MAX II device internal timing microparameters for logic elements (LEs),
input/output elements (IOEs), UFM structures, and MultiTrack
interconnects. The timing values for –3, –4, and –5 speed grades shown in
Tables 5–15
–6 and –7 speed grade values are based on an EPM570Z device target.
For more explanations and descriptions about each internal timing
microparameters symbol, refer to the
Devices
Min
238
238
208
166
–3 Speed
—
—
—
—
0
Grade
chapter in the MAX II Device Handbook.
Max
571
147
235
857
through
—
—
—
—
—
Min
309
309
271
216
–4 Speed
—
—
—
—
0
Grade
5–22
1,114
Max
742
192
305
—
—
—
—
—
are based on an EPM1270 device target, while
Min
381
381
333
266
–5 Speed
Tables 5–15
—
—
—
—
0
Grade
1,372
Max
914
236
376
Understanding Timing in MAX II
—
—
—
—
—
MAX II Device Handbook, Volume 1
DC and Switching Characteristics
Min
401
401
260
253
through
–6 Speed
—
—
—
—
0
Grade
1,215
1,356
Max
243
380
—
—
—
—
—
5–22
Min
541
541
319
335
—
–7 Speed
—
—
—
0
describe the
Grade
2,247
1,722
Max
305
489
—
—
—
—
—
Unit
5–13
ps
ps
ps
ps
ps
ps
ps
ps
ps