epm2210gm100i Altera Corporation, epm2210gm100i Datasheet
epm2210gm100i
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epm2210gm100i Summary of contents
Page 1
... Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. Altera Corporation Section I. MAX II Device Family Data Sheet ® II devices. The chapters contain feature definitions of the internal Chapter 1 ...
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... Revision History I–2 MAX II Device Handbook Altera Corporation ...
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... Altera Corporation December 2007 Chapter 1. Introduction ® II family of instant-on, non-volatile CPLDs is based on a Low-cost, low-power CPLD Instant-on, non-volatile architecture Standby current as low as 29 µA Provides fast propagation delay and clock-to-output times ...
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... DC and Switching Characteristics Core Version a.b.c variable EPM240Z EPM570Z 240 570 192 440 128 to 240 240 to 570 8,192 8,192 80 160 7.5 9.0 152 152 2.3 2.2 6.5 6.7 MAX II white paper. chapter in Altera Corporation December 2007 ...
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... I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins can be migrated. The Quartus place all pins for you when given a device migration list. Altera Corporation December 2007 shows MAX II device speed-grade offerings. Device – ...
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... Micro Micro FineLine FineLine FineLine BGA BGA BGA BGA 0.5 0 121 289 361 7 × × × × 19 Altera Corporation December 2007 1 ...
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... MAX IIG and MAX IIZ devices only accept 1 their VCCINT pins. The 1.8-V V the device core directly. (2) MAX II devices operate internally at 1.8 V. Referenced This chapter references the following documents: Documents ■ ■ Altera Corporation December 2007 EPM240 EPM570 EPM1270 EPM2210 (2) ) 3.3 V, 2.5 V ...
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... Updated timing numbers in Table 1-1. v1.1 1–6 MAX II Device Handbook, Volume 1 shows the revision history for this chapter. Changes Made through 1–5. section. Core Version a.b.c variable Summary of Changes Updated document with MAX IIZ information. — — — — — — Altera Corporation December 2007 ...
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... The global clock lines can also be used for control signals such as clear, preset, or output enable. Figure 2–1 Altera Corporation March 2008 “Functional Description” on page 2–1 “Logic Array Blocks” on page 2–5 “ ...
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... IOE IOE IOE Logic Logic Element Element Logic Logic Element Element Logic Logic Element Element Logic Logic Element Element MultiTrack Interconnect IOE Logic Element Logic Logic Array Element BLock (LAB) Logic Element Logic Element chapter in the MAX II Altera Corporation March 2008 ...
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... UFM Blocks EPM240 1 EPM570 1 EPM1270 1 EPM2210 1 Note to Table 2–1: (1) The width is the number of LAB columns in length. Altera Corporation March 2008 shows the number of LAB rows and columns in each device, as LAB Rows LAB Columns Long LAB Rows MAX II Device Handbook, Volume 1 ...
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... For EPM240 devices, the CFM and UFM blocks are located on the left side of the device. 2–4Core Version a.b.c variable MAX II Device Handbook, Volume 1 shows a floorplan of a MAX II device. Note (1) UFM Block CFM Block Logic Array Blocks 2 GCLK Inputs Altera Corporation March 2008 ...
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... LAB or IOE DirectLink interconnect to adjacent LAB or IOE Logic Element Note to Figure 2–3: (1) Only from LABs adjacent to IOEs. Altera Corporation March 2008 ® II software places associated logic shows the MAX II LAB. Row Interconnect LE0 LE1 LE2 LE3 LE4 LE5 LE6 ...
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... Version a.b.c variable MAX II Device Handbook, Volume 1 Figure 2–4 shows the DirectLink connection. LE0 LE1 LE2 LE3 LE4 LE5 LE6 LE7 Local LE8 LE9 Logic Element LAB DirectLink interconnect from right LAB or IOE output DirectLink interconnect to right Altera Corporation March 2008 ...
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... LAB Column Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local labclk1 Interconnect Altera Corporation March 2008 Figure 2–5 shows the LAB control signal generation circuit. labclkena2 labclkena1 syncload labclk2 asyncload or labpre MAX II Architecture labclr2 addnsub labclr1 synclr 2– ...
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... Load and Chain Clear Logic Carry-Out0 Carry-Out1 LAB Carry-Out Programmable Register LUT chain routing to next LE Row, column, PRN/ALD and DirectLink D Q routing ADATA ENA CLRN Row, column, and DirectLink routing Local routing Register chain Register output Feedback Altera Corporation March 2008 ...
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... LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry- The Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions. Altera Corporation March 2008 MAX II Architecture “MultiTrack for more information about LUT chain and MAX II Device Handbook, Volume 1 2– ...
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... LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. 2–10Core Version a.b.c variable MAX II Device Handbook, Volume 1 “Normal Mode” “Dynamic Arithmetic Mode” Figure 2–7). The Altera Corporation March 2008 ...
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... For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry in0 or data1 + data2 + carry-in1 Altera Corporation March 2008 sload sclear (LAB Wide) (LAB Wide) Register chain ...
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... Wide) ena (LAB Wide) aclr (LAB Wide) Register Feedback Carry-Out1 aload ALD/PRE ADATA Row, column, and Q direct link routing D Row, column, and ENA direct link routing CLRN Local routing LUT chain connection Register chain output Altera Corporation March 2008 ...
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... The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. Altera Corporation March 2008 shows the carry-select circuitry in an LAB for a 10-bit full MAX II Device Handbook, Volume 1 MAX II Architecture 2– ...
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... A carry chain can extend horizontally up to one full LAB row, but does not extend between LAB rows. 2–14Core Version a.b.c variable MAX II Device Handbook, Volume 1 LAB Carry-In Carry-In0 Carry-In1 data1 data2 To top of adjacent LAB LUT Sum LUT LUT LUT Carry-Out0 Carry-Out1 Altera Corporation March 2008 ...
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... The DirectLink interconnect allows an LAB to drive into the local interconnect of its left and right neighbors. The DirectLink interconnect provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. Altera Corporation March 2008 DirectLink interconnects between LABs R4 interconnects traversing four LABs to the right or left MAX II Architecture 2– ...
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... This pattern is repeated for every LAB in the LAB row. 2–16Core Version a.b.c variable MAX II Device Handbook, Volume 1 Adjacent LAB can drive onto another C4 Column Interconnects (1) LAB’s R4 Interconnect LAB Primary LAB Neighbor LAB (2) Neighbor Figure 2–10 shows R4 R4 Interconnect Driving Right Altera Corporation March 2008 ...
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... LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. interconnects. Altera Corporation March 2008 LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four LABs and down direction Figure 2– ...
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... MAX II Device Handbook, Volume 1 Local Interconnect Routing Among LEs in the LAB LE0 LUT Chain Routing to Adjacent LE LE1 Local LE2 Interconnect LE3 LE4 LE5 LE6 LE7 LE8 LE9 shows the C4 interconnect connections from an LAB in a Register Chain Routing to Adjacent LE's Register Input Altera Corporation March 2008 ...
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... Figure 2–12. C4 Interconnect Connections Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 2–12: (1) Each C4 interconnect can drive either up or down four rows. Altera Corporation March 2008 Note (1) Local Interconnect MAX II Architecture C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect ...
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... Figure 2–13. Altera Corporation March 2008 ...
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... LAB column clock buffers shown in Figure LAB clock signals and one LAB clear signal. Other control signal types route from the global clock network into the LAB local interconnect. See “LAB Control Signals” on page 2–6 Altera Corporation March 2008 GCLK0 GCLK1 GCLK2 ...
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... LAB column clocks in I/O block regions provide high fan-out output enable signals. (2) LAB column clocks drive to the UFM block. 2–22Core Version a.b.c variable MAX II Device Handbook, Volume 1 Note ( UFM Block (2) CFM Block LAB Column clock[3.. I/O Block Region Altera Corporation March 2008 ...
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... OSC_ENA ARCLK ARSHFT ARDin DRDin DRCLK DRSHFT Altera Corporation March 2008 Non-volatile storage up to 16-bit wide and 8,192 total bits Two sectors for partitioned sector erase Built-in internal oscillator that optionally drives logic array Program, erase, and busy signals Auto-increment addressing ...
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... Version a.b.c variable MAX II Device Handbook, Volume 1 Device Total Bits Sectors 8,192 (4,096 bits/sector) Figure 2–15, the dedicated circuitry within the UFM block Using User Flash Memory in MAX II Devices Table 2–3 Address Bits Data Width chapter in the Altera Corporation March 2008 ...
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... LAB rows). The UFM signals can also be driven from global clocks, GCLK[3..0]. The interface region for the EPM240 device is shown in EPM2210 devices are shown in Altera Corporation March 2008 chapter in the MAX II Device Handbook. Figures 2–1 and 2–2. The UFM block for the Figure 2– ...
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... The UFM block inputs and outputs can drive to/from all types of interconnects, not only DirectLink interconnects from adjacent row LABs. 2–26Core Version a.b.c variable MAX II Device Handbook, Volume 1 Note (1) CFM Block UFM Block PROGRAM ERASE OSC_ENA RTP_BUSY DRDin DRCLK DRSHFT ARin ARCLK ARSHFT DRDout OSC BUSY LAB LAB LAB Altera Corporation March 2008 ...
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... The MAX IIG and MAX IIZ devices use external 1.8-V supply. The 1.8 Altera Corporation March 2008 CFM Block RTP_BUSY BUSY OSC DRDout ...
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... Tri-state buffers with individual output enable control Bus-hold circuitry Programmable pull-up resistors in user mode Unique output enable per pin Open-drain outputs Schmitt trigger inputs Fast I/O connection Programmable input delay 1.8-V Core Voltage MAX IIG or MAX IIZ Device Figure 2–19 shows Altera Corporation March 2008 ...
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... I/O connection. Figure 2–19. MAX II IOE Structure Data_in Fast_out Data_out OE Note to Figure 2–19: (1) Available in EPM1270 and EPM2210 devices only. Altera Corporation March 2008 Figures DEV_OE Optional PCI Clamp ( CCIO Drive Strength Control Open-Drain Output Slew Control ...
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... The row I/O blocks drive row, column, or DirectLink interconnects. The column I/O blocks drive column interconnects. Figure 2–20 2–30Core Version a.b.c variable MAX II Device Handbook, Volume 1 shows how a row I/O block connects to the logic array. Altera Corporation March 2008 ...
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... Direct Link Interconnect to Adjacent LAB LAB Local Interconnect Note to Figure 2–20: (1) Each of the seven IOEs in the row I/O block can have one data_out or fast_out output, one OE output, and one data_in input. Altera Corporation March 2008 Note (1) C4 Interconnects I/O Block Local Interconnect data_out [6..0] 7 [6..0] 7 fast_out [6 ...
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... MAX II Device Handbook, Volume 1 shows how a column I/O block connects to the logic array. Note (1) Column I/O Block OE fast_out [3..0] [3.. Fast I/O Interconnect LAB Column Path Clock [3..0] LAB LAB Local Interconnect Column I/O Block Contains IOEs data_in [3..0] 4 LAB LAB Local Interconnect C4 Interconnects Altera Corporation March 2008 ...
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... Table 2–4. MAX II I/O Standards 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI Note to (1) The EPM240 and EPM570 devices support two I/O banks, as shown in Figure standards shown in and banks. Altera Corporation March 2008 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI describes the I/O standards supported by MAX II devices. I/O Standard Type Single-ended Single-ended ...
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... Version a.b.c variable MAX II Device Handbook, Volume 1 Notes (1), (2) All I/O Banks Support ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS 2–23. Each of these banks support all of the LVTTL and LVCMOS Table 2–4. PCI I/O is supported in Bank 3. Bank 3 I/O Bank 2 Altera Corporation March 2008 ...
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... The JTAG pins for MAX II devices are dedicated pins that cannot be used as regular I/O pins. The pins TMS, TDI, TDO, and TCK support all the I/O standards shown in reside in Bank 1 for all MAX II devices and their I/O standard support is controlled by the V Altera Corporation March 2008 Notes (1), I/O Bank 2 All I/O Banks Support ■ ...
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... All Speed Grades –3 Speed Grade All Speed Grades –3 Speed Grade The TCK input is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all I/O standards. Table 2–5 shows the MAX II 66-MHz PCI Altera Corporation March 2008 ...
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... I/O standards with drive strength control. The Quartus II software uses the maximum current strength as the default setting. The PCI I/O standard is always set with no alternate setting. Table 2–6. Programmable Drive Strength 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS Altera Corporation March 2008 Table 2–6 shows the possible settings for the I /I I/O Standard OH ...
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... V where the V maximum is specified by the I/O standard. For 2.5-V OL LVTTL/LVCMOS, the I condition 0.7 V. OUT Note (1) (Part Current Strength Setting (mA OUT maximum, OUT OL = 1.7 V and the I condition is OUT OL Altera Corporation March 2008 ...
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... However, a path where a pin drives a register through long routing or through combinational logic may not require the delay to achieve a zero hold time. The Quartus II software uses this delay to ensure zero hold times when needed. Altera Corporation March 2008 DC and Switching Characteristics The programmable pull-up resistor feature should not be used at the same time as the bus-hold feature on a given I/O pin ...
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... V including the overshoot, disable the PCI clamping diode. AN 428: MAX II CPLD Design Output Signal 1.8 V 2.5 V 3.3 V 5.0 V — — — — v — — — — — ( (6) (6) (7) from rising above 4 Guidelines. Altera Corporation March 2008 ...
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... Removed Note 2 from Table 2-7. v1.3 December 2004 Added a paragraph to page 2-15. v1.2 June 2004 v1.1 Added CFM acronym. Corrected Figure 2-19. Altera Corporation March 2008 AN 428: MAX II CPLD Design Guidelines DC and Switching Characteristics Handbook Hot Socketing and Power-On Reset in MAX II Devices MAX II Device Handbook Using User Flash Memory in MAX II Devices Device Handbook shows the revision history for this chapter ...
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... Document Revision History 2–42Core Version a.b.c variable MAX II Device Handbook, Volume 1 Altera Corporation March 2008 ...
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... SAMPLE/PRELOAD 00 0000 0101 (1) EXTEST 00 0000 1111 BYPASS 11 1111 1111 Altera Corporation December 2007 Chapter 3. JTAG and In-System Programmability “IEEE Std. 1149.1 (JTAG) Boundary-Scan Support” on page 3–1 “In System Programmability” on page 3–5 ® II devices provide Joint Test Action Group (JTAG) CCINT amount of time has passed ...
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... JTAG port. Unsupported JTAG instructions should not be issued to the MAX II device as this may put the device into an unknown state, requiring a power cycle to recover device operation. Core Version a.b.c variable Description to be serially shifted out of TDO. ® website at Altera Corporation December 2007 ...
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... For JTAG AC characteristics, refer to the chapter in the MAX II Device Handbook. f For more information about JTAG BST, refer to the Boundary-Scan Testing for MAX II Devices Handbook. Altera Corporation December 2007 Tables 3–2 Device Boundary-Scan Register Length Binary IDCODE (32 Bits) (1) Manufacturer ...
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... JTAG block as a parallel flash loader, with the Quartus II software, to program and verify flash contents provides a fast and cost-effective means of in-circuit programming during test. being used as a parallel flash loader. 3–4 MAX II Device Handbook, Volume 1 Core Version a.b.c variable Figure 3–1 shows MAX II Altera Corporation December 2007 ...
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... V/2 1.8 V for the MAX IIG and MAX IIZ devices). ISP can be performed anytime after V V CCIO configuration power-up time. By default, during in-system Altera Corporation December 2007 JTAG and In-System Programmability MAX II Device DQ[7..0] A[20..0] ...
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... ISP” on page Using Jam STAPL for ISP via an chapter in the MAX II Device Handbook. Enter ISP—The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. Core Version a.b.c variable CCIO 3–8. Altera Corporation December 2007 ...
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... Erase + Program (10 MHz) Verify (1 MHz) Verify (10 MHz) Complete Program Cycle (1 MHz) Complete Program Cycle (10 MHz) Altera Corporation December 2007 Check ID—Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. ...
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... Using Jam STAPL for ISP via an chapter in the MAX II Device Handbook. Real-Time ISP and ISP Clamp for MAX II chapter in the MAX II Device Handbook. ). During this time, the I/O pins are tri-stated and weakly CONFIG . CCIO Core Version a.b.c variable Altera Corporation December 2007 ...
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... Referenced This chapter references the following documents: Documents ■ ■ ■ ■ Altera Corporation December 2007 DC and Switching Characteristics Handbook IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices chapter in the MAX II Device Handbook Real-Time ISP and ISP Clamp for MAX II Devices ...
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... Corrected Figure 3-1. Added CFM acronym. v1.1 3–10 MAX II Device Handbook, Volume 1 shows the revision history for this chapter. Changes Made Table 3–1. Table 3–3 and Table 3–4. section. Core Version a.b.c variable Summary of Changes — — — — — Altera Corporation December 2007 ...
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... Socketing special design requirements. The following are hot-socketing specifications: Specifications ■ ■ ■ Altera Corporation December 2007 Chapter 4. Hot Socketing and Power-On Reset in MAX II ® II devices offer hot socketing, also known as hot plug-in or hot Board or device insertion and removal Support for any power-up sequence Non-intrusive I/O buffers to system buses during hot insertion “ ...
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... I/O pin on the device. The AC Core Version a.b.c variable ), simplifying the system-level for information about turn- Power Supplies CCINT and V pins in any CCIO CCINT | < 300 μA. IOPIN | < for IOPIN Altera Corporation December 2007 ...
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... SRAM logic. The weak pull-up resistor (R) from the I/O pin to V floating. The 3.3-V tolerance control circuit permits the I/O pins to be Altera Corporation December 2007 Hot Socketing and Power-On Reset in MAX II Devices or V ...
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... Larger of VCCIO or VPAD well 4–3) shows the ESD current discharge path during a positive ESD Core Version a.b.c variable are powered, and it prevents CCINT Using MAX II Devices Ensures 3.3-V Tolerance and Hot-Socket The Larger of Protection VCCIO or VPAD VCCIO substrate Altera Corporation December 2007 ...
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... When the I/O pin receives a negative ESD zap at the pin that is less than –0 the voltage drop across a diode), the intrinsic P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current path is from GND to the I/O pin, as shown in Altera Corporation December 2007 Hot Socketing and Power-On Reset in MAX II Devices Source ...
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... CCINT and begins SRAM download at an approximate voltage of 1 and Switching Characteristics Core Version a.b.c variable I GND and V voltage CCINT CCIO voltage level to detect a CCINT in CONFIG Altera Corporation December 2007 ...
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... CCINT restarts and the device begins to operate after t Figure 4–5 MAX IIZ devices during power-up into user mode and from user mode to power-down or brown-out. Altera Corporation December 2007 Hot Socketing and Power-On Reset in MAX II Devices is powered more than t CCIO (but not V ...
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... CONFIG User Mode Tri-State Operation CCINT Core Version a.b.c variable Notes (1), (2) Device Resets the SRAM and Tri-States I/O Pins Device Resets the SRAM and Tri-States I/O Pins CCINT t CONFIG User Mode Operation profile shown. If not, t stretches CONFIG Altera Corporation December 2007 ...
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... Updated Figure 4-5. June 2004 Corrected Figure 4-2. v1.1 Altera Corporation December 2007 Hot Socketing and Power-On Reset in MAX II Devices After SRAM configuration, all registers in the device are cleared and released into user function before I/O tri-states are released. To release clears after tri-states are released, use the DEV_CLRn pin option ...
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... Document Revision History 4–10 MAX II Device Handbook, Volume 1 Core Version a.b.c variable Altera Corporation December 2007 ...
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... DC output current, per pin OUT (4) T Storage temperature STG T Ambient temperature AMB Altera Corporation July 2008 Chapter 5. DC and Switching “Operating Conditions” on page 5–1 “Power Consumption” on page 5–10 “Timing Model and Specifications” on page 5–10 through 5–12 provide information about absolute maximum ...
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... MAX II devices MAX II devices MAX IIG and MAX IIZ devices — — — — (2), (3), (4) — (Part Maximum Unit — 135 °C Minimum Maximum Unit 3.00 3.60 V 2.375 2.625 V 1.71 1.89 V 3.00 3.60 V 2.375 2.675 V 1.71 1.89 V 1.425 1.575 V –0.5 4 CCIO Altera Corporation July 2008 ...
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... Table 5–3. MAX II Device Programming/Erasure Specifications Parameter Erase and reprogram cycles : Note to Table 5–3 (1) This specification applies to the UFM and configuration flash memory (CFM) blocks. Altera Corporation July 2008 Conditions Commercial range (5) Industrial range (6) Extended range chapter in the MAX II Device Handbook. ...
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... V (7) CCIO Typical Maximum Unit — 10 µA — 10 µA 12 — — 150 µA 32 210 µA 400 — mV 190 — — — mA — 25 kΩ — 40 kΩ — 60 kΩ — 95 kΩ Altera Corporation July 2008 ...
Page 75
... The TCK input is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all I/O (5) standards. (6) This is a peak current value with a maximum duration of t (7) Pin pull-up resistance values will lower if an external source drives the pin higher than V Altera Corporation July 2008 Note (1) (Part Conditions Minimum — ...
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... MAX II device family I/O standard (Part Conditions Minimum — — — Characteristics OL (Maximum Drive Strength) 3.3-V VCCIO 2.5-V VCCIO 1.8-V VCCIO 1.5-V VCCIO 1.0 1.5 2.0 2.5 3.0 3.5 Voltage (V) Characteristics OL (Minimum Drive Strength) 3.3-V VCCIO 2.5-V VCCIO 1.8-V VCCIO 1.5-V VCCIO 1.0 1.5 2.0 2.5 3.0 3.5 Voltage (V) Maximum Unit 3.0 3.6 1.7 4.0 –0.5 0.8 Altera Corporation July 2008 ...
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... High-level output voltage OH V Low-level output voltage OL Table 5–8. 1.8-V I/O Specifications (Part Symbol Parameter V I/O supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL Altera Corporation July 2008 DC and Switching Characteristics (Part Conditions Minimum 2 –4 mA ( — OL Conditions Minimum 3 ...
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... Minimum Maximum 1.425 1.575 ( 0.3 CCIO CCIO –0.3 0.35 × V CCIO — CCIO 0.25 × V — CCIO maximum of 4.0, IH Maximum Unit 3.3 3 0.5 V — CCIO 0.3 × — CCIO V — — 0.1 × — CCIO Altera Corporation July 2008 Unit V V Unit ...
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... EPM570 400 µs EPM1270 400 µs EPM2210 500 µs (2) For more information about POR trigger voltage, refer to the chapter in the MAX II Device Handbook. Altera Corporation July 2008 shows the MAX II device family bus hold specifications. V 1.5 V 1.8 V Min Max Min Max ...
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... To Adjacent LE Register Delays Data-Out chapter in the MAX II Device Handbook for more chapter in the chapter in ® II Figure 5–2. Output and Output Enable Data Delay t IODR t IOE Output Routing Output Delay Delay FASTIO I/O Pin Understanding Timing in Altera Corporation July 2008 ...
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... These numbers reflect the actual performance of the device under the worst-case voltage and junction temperature conditions. Table 5–13. MAX II Device Timing Model Status EPM240 EPM240Z EPM570 EPM570Z EPM1270 EPM2210 Note to (1) Altera Corporation July 2008 ® II software issues an informational message during the design Device Preliminary — v (1) — v (1) — ...
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... Performance –4 –5 –6 –7 Speed Speed Speed Grade Grade Grade 201.1 184.1 123.5 125.8 83.2 83.2 8.0 9.3 17.4 17.3 9.0 11.4 12.5 22.8 6.6 8.2 9.0 15.0 6.6 8.2 9.2 15.0 10.0 10.0 10.0 8.0 8.0 9.7 9.7 (4) (4) (4) (4) (5) 100 (5) 100 (5) 100 (5) Altera Corporation July 2008 Unit MHz MHz MHz MHz MHz kHz ...
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... LE register clock-to- CO output delay t Minimum clock high or CLKHL low time t Register control delay C Altera Corporation July 2008 Tables 5–15 through 5–22 are based on an EPM1270 device target, while chapter in the MAX II Device Handbook. –3 Speed –4 Speed –5 Speed Grade ...
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... GLOB Altera Corporation July 2008 Unit ...
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... LVTTL 16 mA — — 2.5-V LVTTL 14 mA — — 3.3-V PCI 20 mA — Altera Corporation July 2008 through 5–20 show the adder delays for t –4 Speed –5 Speed Grade Grade Max Min Max Min Max 0 — 0 — ...
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... Speed Grade Grade Unit Min Max Min Max — 1,433 — 1,446 ps — 1,332 — 1,345 ps — 1,433 — 1,446 ps — 1,332 — 1,345 ps — 213 — 208 ps — 166 — 161 ps — 1,332 — 1,345 ps Altera Corporation July 2008 ...
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... DDS in setup to data register clock t Data register data 20 DDH in hold from data register clock t Program signal data clock hold time Altera Corporation July 2008 –4 Speed –5 Speed Grade Grade Max Min Max Min Max — 100 — 100 — ...
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... Unit Min Max Min Max — 960 — 960 ns 20 — 20 — ns — 100 — 100 µs 0 — 0 — ns — 960 — 960 ns 20 — 20 — ns — 500 — 500 ms — 5 — 180 — 180 — ns Altera Corporation July 2008 ...
Page 89
... UFM block timing parameters shown in Figure 5–3. UFM Read Waveforms ARShft t ACLK t ASU ARClk ARDin t DRShft ADS DRClk DRDin DRDout OSC_ENA Program Erase Busy Altera Corporation July 2008 –4 Speed –5 Speed Grade Grade Max Min Max Min Max 65 — 65 — 65 — 250 — ...
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... OSC_ENA Program Erase Busy 5–20Core Version a.b.c variable MAX II Device Handbook, Volume ADH 16 Data Bits t t DCLK DSS t DDH t DDS 9 Address Bits ADH t OSCS DSH t t OSCH OSCS PPMX t OSCH EPMX Altera Corporation July 2008 ...
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... I/O timing using standards other than LVTTL or for different drive strengths, use the I/O standard input and output delay adders in Tables 5–27 f For more information about each external timing parameters symbol, refer to the MAX II Device Handbook. Altera Corporation July 2008 –4 Speed –5 Speed Grade Grade Min ...
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... Speed Grade Grade Max Min Max Min Max 7.5 — 7.9 — 12.0 5.9 — 5.8 — 7.8 — 2.8 — 4.7 — — 0 — 0 — 6.9 2.0 7.7 2.0 10.5 — 253 — 335 — — 253 — 335 — — 5.4 — 8.1 — Altera Corporation July 2008 Unit ...
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... Best case 10 pF — PD2 pin-to-pin delay through 1 LUT t Global — 1.2 SU clock setup time Altera Corporation July 2008 –3 Speed –4 Speed –5 Speed Grade Grade Grade Min Max Min Max Min — 304.0 — 247.5 — ...
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... Speed –7 Speed Grade Grade Min Max Min Max — 0 — 0 — 7.1 2.0 6.1 2.0 7.6 — 253 — 335 — — 253 — 335 — — 5.4 — 8.1 — — 184.1 — 123.5 MHz Altera Corporation July 2008 Unit ...
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... Table 5–25 (1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. Altera Corporation July 2008 shows the external I/O timing parameters for EPM1270 –3 Speed Grade – ...
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... Speed Grade Unit Max Min Max 9.1 — 11.2 ns 4.8 — 5.9 ns — 1.9 — ns — 0.0 — ns 6.0 2.0 7.4 ns — 266 — ps — 266 — ps — 5.0 — ns 247.5 — 201.1 MHz Altera Corporation July 2008 ...
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... LVTTL Without — Schmitt Trigger 1.5-V LVTTL Without — Schmitt Trigger 3.3-V PCI Without — Schmitt Trigger Altera Corporation July 2008 through 5–31 show the adder delays associated with I/O pins Tables 5–27 through 5–33 through 5–26 I/O standard other than 3.3-V LVTTL and t CO – ...
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... Altera Corporation July 2008 Unit Unit ...
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... Tables 5–32 standard I/O pins in MAX II devices. Table 5–32. MAX II Maximum Input Clock Rate for I/O (Part Standard 3.3-V LVTTL Without Schmitt Trigger With Schmitt Trigger Altera Corporation July 2008 Adders for Slow Slew Rate OD –4 Speed –5 Speed Grade Grade Max Min ...
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... MHz 150 150 MHz 304 304 MHz –7 Speed Unit Grade Grade 304 304 MHz 304 304 MHz 220 220 MHz 220 220 MHz 200 200 MHz 200 200 MHz 150 150 MHz 304 304 MHz Altera Corporation July 2008 ...
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... TCK clock period for V TCK clock period for V TCK clock period for V t TCK clock high time JCH t TCK clock low time JCL t JTAG port setup time JPSU Altera Corporation July 2008 shows the timing waveforms for the JTAG signals. t JCP t JPSU t JCL t JPCO t ...
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... Unit 10 — ns — — — — — ns — — — and t are maximum JPCO JPZX JPXZ chapter in the MAX II chapter in the chapter in the chapter in the MAX II Device chapter in the MAX II Altera Corporation July 2008 ...
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... Updated Table 5-13. ● Added “Output Drive Characteristics” section. 2 ● Added I C mode and Notes 5 and 6 to Table 5-14. ● Updated timing values to Tables 5-14 through 5-33. Altera Corporation July 2008 shows the revision history for this chapter. Changes Made , Table 5–23 , and Table 5–24 . ...
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... Table 5–35. Document Revision History (Part Date and Document Version December 2004 ● Updated timing Tables 5-2, 5-4, 5-12, and Tables 15-14 v1.2 through 5-34. ● Table 5-31 is new. June 2004 ● Updated timing Tables 5-15 through 5-32. v1.1 5–34Core Version a.b.c variable MAX II Device Handbook, Volume 1 Changes Made Summary of Changes — — Altera Corporation July 2008 ...
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... Printed device pin-outs for MAX II devices are available on the Altera website (www.altera.com). Ordering Figure 6–1 information about a specific package, refer to the Information chapter in the MAX II Device Handbook. Altera Corporation December 2007 Chapter 6. Reference and Ordering Information ® II devices are supported by the Altera ® ...
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... Engineering sample N: Lead-free packaging Speed Grade with 3 being the fastest Operating Temperature ° ° C: Commercial temperature ( ° ° I: Industrial temperature ( 100 C) J ° ° A: Automotive temperature ( 125 J Altera Corporation December 2007 C) ...
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... Figure December 2006 Added document revision history. v1.3 October 2006 Updated Figure 6-1. v1.2 June 2005 v1.1 Removed Dual Marking section. Altera Corporation December 2007 shows the revision history for this chapter. Changes Made section. 6–1. Core Version a.b.c variable Reference and Ordering Information Summary of Changes Updated document with MAX IIZ information ...
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... Document Revision History 6–4 MAX II Device Handbook, Volume 1 Core Version a.b.c variable Altera Corporation December 2007 ...