CY28325PVC-2 Cypress Semiconductor Corp., CY28325PVC-2 Datasheet - Page 13

• Manufacturer Part Number: CY28325PVC-2
• Description: Frequency Timing Generators For PC And Server Motherboards
• Manufacturer: Cypress Semiconductor Corp.

Document #: 38-07119 Rev. *A
Register Summary
Pro_Freq_EN
FS_Override
CPU_FSEL_N,
CPU_FSEL_M
ROCV_FREQ_SEL
ROCV_FREQ_N[7:0],
ROCV_FREQ_M[6:0]
WD_EN
WD_TO_STATUS
WD_TIMER[4:0]
WD_PRE_SCALER
RST_EN_WD
RST_EN_FC
Name
Programmable output frequencies enabled
0 = Disabled (default).
1 = Enabled.
When it is disabled, the operating output frequency will be determined by either the latched value of
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled,
the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M
and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of
FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other
frequency outputs.
When Pro_Freq_EN is cleared or disabled
0 = Select operating frequency by FS input pins (default).
1 = Select operating frequency by SEL bits in SMBus control bytes.
When Pro_Freq_EN is set or enabled
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the latched value of FS input pins (default).
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the programmed value of SEL bits in SMBus control bytes.
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load
whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-
mended to use Word or Block Write to update both registers within the same SMBus bus operation.
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When
FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.
When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits
in SMBus control bytes.
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the
selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0].
When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog
Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, AGP
and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be
used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency
will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0].
Therefore, it is recommended to use Word or Block Write to update both registers within the same
SMBus bus operation.
0 = Stop and reload Watchdog Timer.
1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs.
Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = time-out occurred (Read); Clear WD_TO_STATUS (Write).
These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the
prescaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If
the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog
Timer reaches “0,” it will set the WD_TO_STATUS bit.
0 = 150 ms
1 = 2.5 sec
This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
PRELIMINARY
Description
CY28325-2
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