CY28325 Cypress Semiconductor Corp., CY28325 Datasheet
CY28325
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CY28325 Summary of contents
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... Control GND_PCI VDD_48MHz VDD_AGP 48MHz Note: 24_48MHz 1. Pins marked with [*] have internal pull-up resistors. Pins 2 marked with[^] have internal pull-down resistors. RST# • 3901 North First Street • CY28325-2 4 Chipsets AGP PCI REF APIC 48M [1] SSOP-48 1 ...
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... SMBus Clock Input: Clock pin for serial interface. I/O SMBus Data Input: Data pin for serial interface. O System Reset Output: Open-drain system reset output. (open-d rain) I Current Reference for CPU output: A precision resistor is attached to this pin, which is connected to the internal current reference. CY28325-2 Page ...
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... IREF = 5. 221 1%, IREF = 5. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2.32 mA Reference R, IREF = VDD/(3*Rr 221 1%, IREF = 5. 221 1%, IREF = 5. 221 1%, IREF = 5.00 mA CY28325-2 Output Current IOH = 4*Iref 1. 4*Iref 1. 6*Iref 1. 6*Iref 1. 4*Iref ...
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... Table 1. The Block Write and Block Read protocol is outlined in Table 2, while Table 3 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2h). Descriptions CY28325-2 Output Current 5*Iref 1 ...
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... CY28325-2 Block Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits “00000000” stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read Acknowledge from slave Byte count from slave – ...
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... CPUT_CS_F and CPUC_CS_F are Free-running outputs 0 = CPUT_CS_F and CPUC_CS_F will be disabled when CPU_STOP# is active (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) CY28325-2 Description Pin Description Power-on Default Power-on Default 0 ...
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... IREF multiplier 00 = Ioh is 4 × IREF 01 = Ioh is 5 × IREF 10 = Ioh is 6 × IREF 11 = Ioh is 7 × IREF (Active/Inactive control; IREF multiplier is determined by MULTSEL1 input pin control; IREF multiplier is determined by SW_MULTSEL[0:1] CY28325-2 Pin Description Power-on Default ...
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... PCI clock output drive strength 0 = Normal 1 = High Drive AGP clock output drive strength 0 = Normal 1 = High Drive This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs Disabled 1 = Enabled CY28325-2 Pin Description Pin Description Power-on Default ...
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... Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note: CY28325-2 will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, CY28325-2 will not respond to any attempt to change output frequency via the SMBus control bytes ...
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... The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Programmable output frequencies enabled 0 = Disabled 1 = Enabled CY28325-2 Pin Description Power-on Default ...
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... Reserved. Write with “1” Reserved. Write with “1” Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28325-2 Pin Description Pin Description Pin Description Pin Description Power-on Default Power-on Default X X ...
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... Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. CY28325-2 PLL Gear Constants PCI APIC (G) 34 ...
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... RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs Disabled 1 = Enabled RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs Disabled 1 = Enabled Document #: 38-07119 Rev. ** PRELIMINARY Description CY28325-2 Page ...
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... M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Fixed Value for M-Value Register 93 45 CY28325-2 Range of N-Value Register for Different CPU Frequency 97 - 255 127 - 245 Page ...
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... IN DD For I =6*IRef Configuration OH REF, 24_48MHz, 48 MHz AGP, PCI REF, 24_48MHz, 48 MHz AGP, PCI Three-state 3 3.465V, 2.5V V – 2.625V 3.465V, 2.5V V – 2.625V DD DD CY28325-2 Min. Max. Unit 3.135 3.465 2.375 3.625 22 14.318 14.318 MHz Min. Max. Unit /2 2 ...
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... Measured single ended waveform from 0.14V to 0.56V Measured at Crossover Measured at Crossover t With all outputs running Measured with test loads Measured with test loads Measured with test loads Measured with test loads = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V 49.9 ohm in test circuit. CY28325-2 Min. Max 0.5 2.0 0.5 2.0 0.5 2.0 1 ...
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... Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 AGP-AGP Clock Skew AGP AGP t 5 PCI-PCI Clock Skew PCI PCI t 6 Document #: 38-07119 Rev. ** PRELIMINARY CY28325-2 Page ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges Package Type 48-pin Shrunk Small Outline Package (SSOP) 48-lead Shrunk Small Outline Package O48 CY28325 Operating Range Commercial 51-85061-*C ...
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... Document Title: CY28325-2 FTG for Via Pentium 4 Document Number: 38-07119 REV. ECN NO. Issue Date ** 111733 03/06/02 Document #: 38-07119 Rev. ** PRELIMINARY Chipsets Orig. of Change IKA New Data Sheet Added notes to page 18 CY28325-2 Description of Change Page ...