tda8757hl NXP Semiconductors, tda8757hl Datasheet - Page 20

• Manufacturer Part Number: tda8757hl
• Description: Triple 8-bit Adc 170 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09457
Preliminary data
9.1.6 Divider register
9.1.7 Phase register
Table 9:
Bits ‘Vco1’ and ‘Vco0’ control the VCO gain.
Table 10: VCO gain control
The default programmed value is as follows:
This register controls the PLL frequency. Bits ‘Di8’ to ‘Di0’ are the LSB bits. The
default programmed value is 0110 1001 1000 = 1688.
The MSB bits (‘Di11’, ‘Di10’ and ‘Di9’) and the LSB bit ‘Di0’ have to be programmed
before bits ‘Di8’ to ‘Di1’ in order to have the required divider ratio. Bit ‘Di0’ is used for
the parity divider number (Di0 = 0: even number; Di0 = 1: odd number). It should be
noted that if the I
toggled, then the registers have to be loaded twice to update the divider ratio.
Bit ‘Ckext’ is logic 0 when the PLL clock is used, and logic 1 when the external clock
is used.
Bit ‘Ckrs’ is logic 1 when the synchronization is done with CKREF (see
Bits ‘P4’ to ‘P0’ are used to program the phase shift for the clock pixel.
Z2
0
0
0
0
1
1
1
1
Vco1
0
0
1
1
•
•
Internal resistance = 2.25 k
VCO gain = 70 MHz/V.
VCO register bits
2
Rev. 07 — 28 February 2002
C-bus programming is done in mode 1 and the bit ‘Di0’ has to be
Z1
0
0
1
1
0
0
1
1
Vco0
0
1
0
1
Z0
0
1
0
1
0
1
0
1
VCO gain (MHz/V)
12
20
40
70
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Triple 8-bit ADC 170 Msps
Resistance (k )
high-impedance
9
6.4
4.5
3.2
2.25
1.6
1.1
Pixel clock
frequency range
(MHz)
10 to 20
20 to 40
40 to 85
85 to 170
TDA8757
Figure
3).
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