tda8757hl NXP Semiconductors, tda8757hl Datasheet - Page 15

• Manufacturer Part Number: tda8757hl
• Description: Triple 8-bit Adc 170 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09457
Preliminary data
The reference clock (CKREF) range is between 15 and 150 kHz. Consequently, the
VCO minimum frequency is 12 MHz and the maximum frequency is 170 MHz. The
gain of the VCO part can be controlled through the serial interface, depending on the
frequency range to which the PLL is locked.
Moreover, the PLL may be locked either on the rising or on the falling edge of the
CKREF signal pulses. This choice is made through the serial interface by setting
bit ‘Edge’ in register CONTROL (rising edge when bit ‘Edge’ = 0).
The charge pump current (I
programmable through the serial interface by setting bits ‘Ip2’, ‘Ip1’ and ‘Ip0’ in the
control register (see
Different resistance values (R) for the filter can also be programmed through the
serial interface by setting the bits ‘Z2’, ‘Z1’ and ‘Z0’ in register VCO (see
To have optimal PLL performance, R and I
where:
In the event that several combinations of R and I
of the damping factor (
The combination of R and I
the optimal PLL performance.
where C
values are: C
The COAST signal is used to disconnect the PLL phase frequency detector during
the frame flyback (vertical blanking) or during the unavailability of the CKREF signal.
This signal can normally be derived from the VSYNC signal.
COAST may be set either active HIGH or active LOW by setting bit ‘Vlevel’ in the
control register through the serial interface (Vlevel = 0 when HIGH).
Lim
•
•
•
•
•
=
The result of the product ‘R
The result of the product ‘R
DR
horizontal line frequency of the incoming signal. The setting of this parameter is
performed through the serial interface with bits Di0 to Di11. These bits are present
in the VCO-, divider- and phase registers.
f
K
Table
ref
0
R C
-------------- -
=
= the VCO gain, which depends on the pixel frequency ranges given in
= the frequency of the signal.
PLL
2
0.3
--------------------------------------------------
Z
10.
= the divider ratio, which is the ratio between the pixel frequency and the
Z
and C
Z
---------------------------------------------- -
DR
DR
= 68 nF and C
P
K
Rev. 07 — 28 February 2002
PLL
PLL
are the external capacitors of the PLL loop filter. The recommended
0
K
Table
0
C
f
I
ref
cp
Z
for each combination becomes necessary.
+
8).
cp
C
P
whose damping factor is the closest to 1.5, generates
P
= 150 pF.
cp
I
I
) enables an increase of PLL bandwidth. It is
cp
cp
’ is smaller than a determined limit (Lim)
’ is as close as possible to this limit (Lim).
cp
must be chosen so that:
cp
give the same result, a calculation
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Triple 8-bit ADC 170 Msps
TDA8757
Table
15 of 37
9).
(1)
(2)