rtc-4553ac Epson Electronics America, Inc., rtc-4553ac Datasheet - Page 23

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rtc-4553ac

Manufacturer Part Number
rtc-4553ac
Description
Real Time Clock Module
Manufacturer
Epson Electronics America, Inc.
Datasheet
RTC – 4553AC
Additional information
When CS0 is "L", the serial address data input at S
selected, and data are written as shown below.
The selected counter register or RAM address data are output in the following cycle from S
(5) System reset
Time/calendar (CNTR = "0")
Control register and SRAM
WR = "H" is taken in on the 8th pulse leading edge of SCK ., the counter control register or RAM address is
SCK trailing edge.
The SYSR (system reset) condition can be released by causing an up transition of CS0 and a down
transition of SCK .
SYSR bit
SCK
CSo
WR
S
IN
Don't care
A0
Address (1111)
A1 A2
A3
Page - 20
Counter data are incremented.
Example
Address and 4-bit data are written.
D0 D1 D2 D3
Data (0111)
incrementing
Data before
IN
0
8
System reset
are read at the leading edge of SCK . Next, when
Don't care
incrementing steps
Number of
4
3
Don't care
11 (10-digit is carried
automatically.)
incrementing
Release
Data after
4
OUT
, in sync with the
MQ - 342 - 01

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