rtc-4553ac Epson Electronics America, Inc., rtc-4553ac Datasheet - Page 18

• Manufacturer Part Number: rtc-4553ac
• Description: Real Time Clock Module
• Manufacturer: Epson Electronics America, Inc.

RTC – 4553AC
8.3.6. CS1 and CS0 Operation
8.3.7. System Power Down During Interface Operation
8.3.8. Power Supply and CS1 Operation
(7) Time/calendar read example using BUSY bit down transition
When designing a floating arrangement, take the following into consideration. CS0 can be floating while CS1
= "L", but CS1 can never be floating. (Otherwise a through current would flow, leading to increased current
consumption during operation on backup battery power.) When CS1 = "L", input is disabled, and S
When the system power goes down during interface operation with the CPU, causing CS1 to become "L", the
incomplete data will be invalid. Immediately after system power restoration, when CS1 has become "H", the
output data from S
When the system power is shut down, V
set to "L" before V
set to "H" before V
TP
System power on/off time chart
NO
NO
OUT
Read time/calendar
are at high impedance.
BUSY = 1?
PONC=0?
PONC=0?
MS
MS
START
END
0
1
OUT
DD
DD
YES
CS
CS
WR
TP
YES
S
SCK
S
crosses point <B>.
0
0
IN
OUT
crosses point <A> in the diagram below. When system power is restored, CS1 must be
OUT
1
0
are undefined for one cycle.
If PONC = "1", initialization was
carried out and data must be set
again
System power
V
CS
NO
Time and calendar read interval is 996 ms.
DD
1
DD
falls to the battery voltage. When used at V
<A> V
Page - 15
DD
-20 %
Access disabled
Power down
<B>
To internal circuits
To internal circuits
To internal circuits
To internal circuits
From internal circuits
From internal circuits
Battery voltage
5 V
DD
±10%, CS1 must be
MQ - 342 - 01
OUT
and