rtc-4553ac Epson Electronics America, Inc., rtc-4553ac Datasheet - Page 11

• Manufacturer Part Number: rtc-4553ac
• Description: Real Time Clock Module
• Manufacturer: Epson Electronics America, Inc.

RTC – 4553AC
8.1.2. Register Bit Functions
(Power-on-clear detection)
(30 seconds adjustment)
(Timing pulse selection)
Day of the week digit
Second to year digit
(Mode selection)
User RAM area
Bit marked "
Bit marked "
(Counter reset)
(System reset)
Bit marked "0"
Bit name
MS0, MS1
Year digit
PM/ AM
24/ 12
30ADJ
CNTR
PONC
SYSR
TEST
Busy
TPS
"
"
Unused bit that cannot be written. Always read as "0".
BCD code. Data are written using increment method.
"1" indicates PM and "0" indicates AM. This bit can be read also when 24-hour format is
selected (24/12=1). (AM: 00:00 to 11:59, PM: 12:00 to 23:59)
To be coded as 7-base counter.
Example
Automatic leap year compensation up to 2099
30
Bit for selecting reference signal output
waveform.
Note 1/10 Hz is not output for 10 seconds
Setting this bit to "1" performs 30 second adjustment.
The bit automatically resets when 30 second adjustment is completed (after 76.3 s).
Setting this bit to "1" resets the time and calendar counters.
24-hour or 12-hour format selection bit. When set to "1", 24-hour format is used. When set
to "0", 12-hour format is used.
Used when reading/writing time and calendar counter data. Set to "1" when carry occurs.
At power-on, the power-on-clear function automatically sets this bit to "1". This has the
same effect as data initialization.
When PONC is "1", data must be set. First clear this bit (this can be done by writing "1" to
SYSR and then releasing system reset) and then set the time/calendar counters.
Cannot be written. When read, the data are undefined.
Can be written but must always be set to "0".
At SYSR = "1" all logic bits are initialized. The SYSR bit is reset to "0" by causing an up
transition of CS0 and a down transition of SCK.
Epson test bit. Must be set to "0".
These 2 bits serve for mode selection.
Time/calendar counters
Control registers
User RAM area
Time/calendar counters
Control registers
User RAM area
BUSY bit
Coded day of the week Sun. Mon. Tue. Wed. Thu.
MS1
0
0
1
1
4 bit SRAM
after power-on or system reset (output is
"L").
0
1
Register
Register
MS0
Data
0
1
0
1
No carry
Mode
Carry
Mode name
Mode 0
Mode 0
Mode 1
Mode 2
Page - 8
Time/calendar counter read/write possible
Time/calendar counter read/write prohibited
00- year, 01-month, 01-day, AM 12-hour,
00-minute, 00- second, 0-day of the week
All "0" (PONC = "1")
Undefined
00- year, 01-month, 01-day, AM 12-hour,
00-minute, 00- second, 0-day of the week
All "0" (SYSR = "1")
Undefined
Time/calendar counters and control
registers 1 - 3
Time/calendar counters and control
registers 1 - 3
User RAM area (RA
register 3
User RAM area (RA
control register 3
0
1
Function
Meaning
Data
Data
Content
2
0
60
- RA
- RA
59
TPS bit
119
3
) and control
) and
0
1
4
1024 Hz (976.5 s)
1/10 Hz (10 s)
Frequency (cycle time)
Fri.
5
Sat.
MQ - 342 - 01
6