sg25672rddr6h2bgic ETC-unknow, sg25672rddr6h2bgic Datasheet - Page 4

• Manufacturer Part Number: sg25672rddr6h2bgic
• Description: Dram Module Ddr Sdram 2gbyte 184rdimm
• Manufacturer: ETC-unknow

Pin Description Table
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Symbol
CK0
CK0#
CKE0, CKE1
CS0#, CS1#
RAS#, CAS#,
WE#
BA0, BA1
A0~A9,
A10/AP,
A11~A12
DQ0~DQ63
CB0~CB7
DQS0~DQS17
SA0~SA2
SDA
SCL
RESET#
V
V
V
V
NC
DD,
REF
DDQ
DDSPD
V
SS
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
LVTTL
LVTTL
LVTTL
LV-
CMOS
Supply
Supply
Supply
Supply
-
Polarity
Positive
Edge
Negative
Edge
Active High
Active Low
Active Low
-
-
-
Negative &
Positive
Edge
-
-
-
Active Low
-
-
-
-
-
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
(All DDR SDRAM addr/cntl inputs are sampled on the rising edge of their associated clocks.)
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM
PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deacti-
vating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the oper-
ations to be executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11-A12 defines the column address (CA0-
CA9, CA11-CA12) when sampled at the rising clock edge. In addition to the column address,
A10/AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If
AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is
low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of
BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
Data strobe for input and output data.
These signals are tied on the system to either V
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must
be connected on the system board from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected on the system board from the SCL bus line to V
This signal is asynchronous and driven low to the register to guarantee that the register outputs
are low.
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for SSTL2 inputs.
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which
supports both 2.3 Volt and 3.3 Volt operation).
No Connect.
SG25672RDDR6H2BGUU
SS
or V
DD
DD
to act as a pullup.
to configure the serial SPD.
DD
to act as a pullup.
July 5, 2007
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