cs49329 Cirrus Logic, Inc., cs49329 Datasheet - Page 84

• Manufacturer Part Number: cs49329
• Description: Multi-standard Audio Decoder Family
• Manufacturer: Cirrus Logic, Inc.

RESET—Master Reset Input: Pin 36
SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port Type
Select: Pin 19
EXTMEM, GPIO8—External Memory Chip Select or General Purpose Input & Output Number 8:
Pin 21
INTREQ, ABOOT—Control Port Interrupt Request, Automatic Boot Enable: Pin 20
AUDATA2—Digital Audio Output 2: Pin 39
AUDATA1—Digital Audio Output 1: Pin 40
AUDATA0—Digital Audio Output 0: Pin 41
MCLK—Audio Master Clock: Pin 44
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Asynchronous active-low master reset input. Reset should be low at power-up to initialize the
CS493XX and to guarantee that the device is not active during initial power-on stabilization
periods. At the rising edge of reset the host interface mode is selected contingent on the state
of the RD, WR and PSEL pins. Additionally, an autoboot sequence can be initiated if a serial
control mode is selected and ABOOT is held low. If reset is low all bidirectional pins are high
impedance inputs. INPUT
In I
serves as the data output pin. In parallel host mode, this pin is sampled at the rising edge of
RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus. In
parallel host mode, after the bus mode has been selected, the pin can function as a general-
purpose input or output pin. At reset this pin acts as one of the mode select pins. It requires a
3.3k Ohm pull-up or pull-down. BIDIRECTIONAL - Default: INPUT
In I
In serial control port mode, this pin can serve as an output to provide the chip-select for an
external byte-wide ROM. In parallel and serial host mode, this pin can also function as a
general-purpose input or output pin. BIDIRECTIONAL - Default: INPUT
Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has
outgoing control data and should be serviced by the host. Also in serial host mode, this signal
initiates an automatic boot cycle from external memory if it is held low through the rising edge
of reset. OPEN DRAIN I/O - Requires 3.3k Ohm Pull-Up
PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM
output defaults to DGND as output until enabled by the DSP software. OUTPUT
PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM
output defaults to DGND as output until enabled by the DSP software. OUTPUT
PCM multi-format digital-audio data output, capable of two-, four-, or six-channel 20-bit output.
This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT
Bidirectional master audio clock. MCLK can be an output from the CS493XX that provides an
oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can be an input at
128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK when SCLK and
LRCLK are driven by the CS493XX. BIDIRECTIONAL - Default: INPUT
2
2
C mode this pin is an OPEN DRAIN I/O and requires a 3.3k Pull-Up
C mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pin
CS49300 Family DSP
DS339F7