cs49329 Cirrus Logic, Inc., cs49329 Datasheet - Page 27

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cs49329

Manufacturer Part Number
cs49329
Description
Multi-standard Audio Decoder Family
Manufacturer
Cirrus Logic, Inc.
Datasheet

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3.
Six typical connection diagrams have been
presented to illustrate using the part with the
different communication modes available. They
are as follows:
Figure 13, "I
Figure 14, "I
page 30
Figure 15, "SPI Control" on page 31
Figure 16, "SPI Control with External Memory" on
page 32
Figure 17, "Intel
33
Figure 18, "Motorola
page 34
The following should be noted when viewing the
typical connection diagrams:
The pins are grouped functionally in each of the
typical connection diagrams. Please be aware that
the CS493XX symbol may appear differently in
each diagram.
The external memory interface is only supported
when a serial communication mode has been
chosen.
The typical connection diagrams demonstrate the
PLL being used (CLKSEL is pulled low). To use
CLKIN as the DSP clock, CLKSEL should be
pulled high. The system designer must be aware
that certain software features may not be available
if external CLKIN is used as the DSP must run
slower when external CLKIN is used. The system
designer should also be aware of additional duty
cycle requirements when using external CLKIN as
a DSP clock. It is highly suggested that the system
designer use the PLL and pull CLKSEL low.
3.1. Multiplexed Pins
The CS493XX family of digital signal processors
(DSPs) incorporate a large amount of flexibility into
a 44 pin package. Because of the high degree of
integration, many of these pins are internally
multiplexed to serve multiple purposes. Some pins
are designed to operate in one mode at power up,
and serve a different purpose when the DSP is
running. Other pins have functionality which can be
controlled by the application running on the DSP.
DS339F7
TYPICAL CONNECTION
DIAGRAMS
2
2
C
C
®
®
®
Control with External Memory" on
Control" on page 29
Parallel Control Mode" on page
®
Parallel Control Mode" on
In order to better explain the behavior of the part,
the pins which are multiplexed have been given
multiple names. Each name is specific to the pin’s
operation in a particular mode.
An example of this would be the use of pin 20 in
one of the serial control modes. During the boot
period of the CS493XX, pin 20 is called ABOOT.
ABOOT is sampled on the rising edge of RESET.
If ABOOT is high the host must download code to
the DSP. If ABOOT is low when sampled, the
CS493XX goes into autoboot mode and loads itself
with code by generating addresses and reading
data on EMAD[7:0]. When the part has been
loaded with code and is running an application,
however, pin 20 is called INTREQ. INTREQ is an
open drain output used to inform the host that the
DSP has an outgoing message which should be
read.
In this document, pins will be referred to by their
functionality.
page 82
lists all of its names. Please refer to this section
when exact pin numbers are in question.
The part has 12 general purpose input and output
(GPIO[11:0])
functionality. While in one of the parallel
communication modes
Communication” on page
to implement the parallel host communication
interface. While in one of the serial host modes
these pins are used to implement an external
memory interface. Alternatively while in one of the
serial host modes these pins could be used for
another general purpose if the application code
has been programmed to support the special
purpose. In this document the pins are referenced
by the name corresponding to their particular use.
Sometimes GPIO[11:0], or some subset thereof, is
used when referring to the pins in a general sense.
3.2. Termination Requirements
The CS493XX incorporates open drain pins which
must be pulled high for proper operation. INTREQ
(pin 20) is always an open drain pin which requires
a pull-up for proper operation. When in the I
serial communication mode, the SCDIO signal (pin
19) is open drain and thus requires a pull-up for
proper operation.
describes each pin of the CS493XX and
Section 12, “Pin Descriptions” on
pins
CS49300 Family DSP
that
(Section 6.2, “Parallel Host
44), these pins are used
all
have
multiple
2
27
C

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