cef830g Hope Microelectronics co., Ltd, cef830g Datasheet - Page 36

• Manufacturer Part Number: cef830g
• Description: Rf42/43 Ism Transmitter
• Manufacturer: Hope Microelectronics co., Ltd

7.2. Microcontroller Clock
The crystal oscillator frequency is divided down internally and may be output to the microcontroller through
GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock
frequency is selectable from one of 8 options, as shown below. Except for the 32.768 kHz option, all other
frequencies are derived by dividing the Crystal Oscillator frequency. The 32.768 kHz clock signal is derived from
an internal RC Oscillator or an external 32 kHz Crystal, depending on which is selected. The GPIO2 default is the
microcontroller clock with a 1 MHz microcontroller clock output.
If the microcontroller clock option is being used there may be the need of a System Clock for the microcontroller
while the RF42/43 is in SLEEP mode. Since the Crystal Oscillator is disabled in SLEEP mode in order to save
current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This
feature is called Enable Low Frequency Clock and is enabled by the enlfc bit. When enlfc = 1 and the chip is in SLEEP
mode then the 32.768 kHz clock will be provided to the microcontroller as the System Clock, regardless of the setting
of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the
microcontroller as the System Clock in all IDLE or TX states. When the chip is commanded to SLEEP mode, the
System Clock will become 32.768 kHz.
Another available feature for the microcontroller clock is the Clock Tail, clkt[1:0]. If the Enable Low Frequency Clock
feature is not enabled (enlfc = 0), then the System Clock to the microcontroller is disabled in SLEEP mode. However, it
may be useful to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdown of the
System Clock signal. Setting the clkt[1:0] field will provide additional cycles of the System Clock before it shuts off.
If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon
as the interrupt is read the state machine will then move to the selected mode. For instance, if the chip is commanded
to Sleep mode but an interrupt has occurred the 30 MHz XTAL will not disable until the interrupt has been cleared.
Add
A0
R/W
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R/W
Function/Descript
Microcontroller
Output Clock
ion
clkt[1:0]
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mclk[2:0]
00
01
10
11
D7
000
001
010
011
100
101
110
111
D6
clkt[1]
Modulation Source
D5
Modulation Source
128 cycles
256 cycles
512 cycles
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0 cycles
clkt[0]
D4
32.768 KHz
30 MHz
15 MHz
10 MHz
4 MHz
3 MHz
2 MHz
1 MHz
enlfc
D3
mclk[2]
D2
R F 4 2 / 4 3
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mclk[1]
D1
mclk[0]
D0
POR
Def.
00h
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