cef830g Hope Microelectronics co., Ltd, cef830g Datasheet - Page 26

• Manufacturer Part Number: cef830g
• Description: Rf42/43 Ism Transmitter
• Manufacturer: Hope Microelectronics co., Ltd

4.2. Modulation Data Source
The RF42/43 may be configured to obtain its modulation data from one of three different sources: FIFO mode,
Direct Mode, and from a PN9 mode. Furthermore, in Direct Mode, the TX modulation data may be obtained from
several different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode
Control 2".
4.3. FIFO Mode
In FIFO mode, the integrated FIFO is used to transmit the data. The FIFO is accessed via "Register 7Fh. FIFO
Access" with burst write capability. The FIFO may be configured specific to the application packet size, etc. (see "6.
Data Handling and Packet Handler" for further information).
When in FIFO mode the chip will automatically exit the TX State when the ipksent interrupt occurs. The chip will
return to any of the other states based on the settings in "Register 07h. Operating Mode and Function Control 1".
For instance, if both the txon and pllon bits are set, the chip will transmit all of the contents of the FIFO and the
ipksent interrupt will occur. When this event occurs the chip will clear the txon bit and return to pllon or Tune Mode. If
no other bits are set in register 07h besides txon initially then the chip will return to the Idle state.
4.4. Direct Mode
For legacy systems that have packet handling within an MCU or other baseband chip, it may not be desirable to
use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. In Direct Mode, the TX
modulation data is applied to an input pin of the chip and processed in ―real time‖ (i.e., not stored in a register for
transmission at a later time). There are various configurations for choosing which pin is used for the TX Data.
Furthermore, an additional input pin is required for the TX Data Clock if GFSK modulation is desired (only the TX Data
input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0] field, and
various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field.
Add
71
The eninv bit in Address 71h will invert the TX Data for testing purposes.
modtyp[1:0]
trclk[1:0]
R/W
R/W
Tel: [phone]
00
01
10
11
00
01
10
11
Function/Descr
Modulation Mode
Control 2
iption
Direct Mode using TX_Data via GPIO pin (GPIO needs programming accordingly also)
TX Data Clock is available via GPIO (GPIO needs programming accordingly as well)
Fax: [phone]
Direct Mode using TX_Data via SDI pin (only when nSEL is high)
TX Data Clock is available via SDO pin (only when nSEL is high)
trclk[1]
D7
trclk[0]
D6
TX Data Clock is available via the nIRQ pin
TX Data Clock Configuration
dtmod
No TX Clock (only for FSK)
D5
PN9 (internally generated)
[1]
Modulation Source
E-mail: [e-mail]
dtmod
FIFO Mode
D4
[0]
eninv
D3
fd[8]
D2
R F 4 2 / 4 3
http://www.hoperf.com
modtyp[1]
D1
modtyp[0]
D0
POR
Def.
23h
26