SC16C754B NXP Semiconductors, SC16C754B Datasheet - Page 8

• Manufacturer Part Number: SC16C754B
• Description: 5 V - 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.)
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 2.
SC16C754B_4
Product data sheet
Symbol
IOW
n.c.
RESET
RIA
RIB
RIC
RID
RTSA
RTSB
RTSC
RTSD
RXA
RXB
RXC
RXD
RXRDY
TXA
TXB
TXC
TXD
TXRDY
Pin
LQFP64 LQFP80 PLCC68
9
-
27
63
19
30
50
5
13
36
44
62
20
29
51
-
8
10
39
41
-
Pin description
11
1, 2, 20,
21, 22,
27, 40,
41, 42,
60, 61,
62, 80
33
78
24
38
64
7
15
47
55
77
25
37
65
34
10
12
50
52
35
…continued
18
31
37
8
28
42
62
14
22
48
56
7
29
41
63
38
17
19
51
53
39
Type
I
-
I
I
O
I
O
O
O
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 04 — 6 October 2008
Description
Input/Output Write strobe (active LOW). A LOW-to-HIGH transition on
IOW will transfer the contents of the data bus (D[7:0]) from the external
CPU to an internal register that is defined by address bits A[2:0] and CSA
and CSD.
not connected
Reset. This pin will reset the internal registers and all the outputs. The
UART transmitter output and the receiver input will be disabled during
reset time. RESET is an active HIGH input.
Ring Indicator (active LOW). These inputs are associated with
individual UART channels, A through D. A logic 0 on these pins indicates
the modem has received a ringing signal from the telephone line. A
LOW-to-HIGH transition on these input pins generates a modem status
interrupt, if enabled. The state of these inputs is reflected in the Modem
Status Register (MSR).
Request to Send (active LOW). These outputs are associated with
individual UART channels, A through D. A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send. Writing a
logic 1 in the Modem Control Register MCR[1] will set this pin to a logic 0,
indicating data is available. After a reset these pins are set to a logic 1.
These pins only affect the transmit and receive operations when
auto-RTS function is enabled via the Enhanced Feature Register
(EFR[6]) for hardware flow control operation.
Receive data input. These inputs are associated with individual serial
channel data to the SC16C754B. During the local loopback mode, these
RX input pins are disabled and TX data is connected to the UART RX
input internally.
Receive Ready (active LOW). RXRDY contains the wire-ORed status of
all four receive channel FIFOs, RXRDY A to RXRDY D. It goes LOW
when the trigger level has been reached or a time-out interrupt occurs. It
goes HIGH when all RX FIFOs are empty and there is an error in RX
FIFO. This pin is associated with LQFP80 and PLCC68 packages only.
Transmit data. These outputs are associated with individual serial
transmit channel data from the SC16C754B. During the local loopback
mode, the TX output pin is disabled and TX data is internally connected
to the UART RX input.
Transmit Ready (active LOW). TXRDY contains the wire-ORed status of
all four transmit channel FIFOs, TXRDY A to TXRDY D. It goes LOW
when there are a trigger level number of spaces available. It goes HIGH
when all four TX buffers are full. This pin is associated with LQFP80 and
PLCC68 packages only.
SC16C754B
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© NXP B.V. 2008. All rights reserved.
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