SC16C754B NXP Semiconductors, SC16C754B Datasheet
SC16C754B
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SC16C754B Summary of contents
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... The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates Mbit/s (3.3 V and 5 V). The SC16C754B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software fl ...
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... V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Description plastic low profile quad flat package; 64 leads; body 7 plastic low profile quad flat package; 80 leads; body 12 plastic leaded chip carrier; 68 leads Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Version 7 1.4 mm SOT414 ...
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... REGISTER SELECT CSA to CSD LOGIC INTA to INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC INTSEL Fig 1. Block diagram of SC16C754B SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs TRANSMIT FIFO REGISTERS FLOW CONTROL LOGIC RECEIVE FIFO REGISTERS FLOW ...
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... CC 5 RTSA INTA 6 CSA 7 8 TXA SC16C754BIBM IOW 9 TXB 10 CSB 11 12 INTB RTSB 13 GND 14 15 DTRB CTSB 16 Pin configuration for LQFP64 Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com 48 DSRD 47 CTSD 46 DTRD 45 GND 44 RTSD 43 INTD 42 CSD 41 TXD 40 IOR 39 TXC 38 CSC 37 INTC 36 RTSC ...
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... V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs SC16C754BIB80 Pin configuration for LQFP80 Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com 60 n.c. 59 DSRD 58 CTSD 57 DTRD 56 GND 55 RTSD 54 INTD 53 CSD 52 TXD 51 IOR 50 TXC ...
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... MCR[7]. A logic 0 (GND) on CLKSEL will latch a logic 1 into MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value. This pin is associated with LQFP80 and PLCC68 packages only. This pin is connected to V internally on LQFP64 package. CC Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com 60 DSRD 59 CTSD 58 ...
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... This pin is connected to GND internally on the LQFP64 package. I Input/Output Read strobe (active LOW). A HIGH-to-LOW transition on IOR will load the contents of an internal register defined by address bits A[2:0] onto the SC16C754B data bus (D[7:0]) for access by external CPU. Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com © ...
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... Enhanced Feature Register (EFR[6]) for hardware flow control operation. I Receive data input. These inputs are associated with individual serial channel data to the SC16C754B. During the local loopback mode, these RX input pins are disabled and TX data is connected to the UART RX input internally. O Receive Ready (active LOW) ...
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... The complete status of each channel of the SC16C754B UART can be read at any time during functional operation by the processor. The SC16C754B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels ...
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... V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs SERIAL PARALLEL RTS CTS FLOW CONTROL PARALLEL SERIAL CTS RTS FLOW CONTROL Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com UART 2 PARALLEL TO SERIAL TX FIFO FLOW CONTROL SERIAL TO PARALLEL RX FIFO FLOW CONTROL 002aaa228 © NXP B.V. 2008. All rights reserved ...
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... When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but it does not send the next byte. When CTS goes from HIGH to LOW, the transmitter begins sending data again. CTS functional timing Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Figure 1 “Block diagram of Stop Start ...
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... Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO. 6.3.1 RX When software flow control operation is enabled, the SC16C754B will compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character is received, transmission is halted after completing transmission of the current character ...
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... PARALLEL-TO-SERIAL Xoff–Xon–Xoff SERIAL-TO-PARALLEL Xon1 WORD Xon2 WORD Xoff1 WORD Xoff2 WORD programmed characters Software flow control example Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com UART2 RECEIVE FIFO data SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon1 WORD Xon2 WORD Xoff1 WORD compare ...
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... Signal RESET functions Reset control RESET RESET RESET RESET RESET Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com st character while UART2 is sending the Xoff Reset state all bits cleared bit 0 is set; all other bits cleared all bits cleared reset to 0001 1101 (1Dh) all bits cleared bit 5 and bit 6 set ...
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... NXP Semiconductors 6.5 Interrupts The SC16C754B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 7:5 and 3:0. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0] ...
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... Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Figure 9 shows interrupt mode operation. IOW / IOR INT PROCESSOR Interrupt mode operation IOW / IOR PROCESSOR Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com IIR IER THR RHR 002aaa230 Figure 10 ...
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... V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs shows TXRDY and RXRDY in DMA mode 0/FIFO disable. TX TXRDY at least one location filled TXRDY FIFO EMPTY Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com RX RXRDY at least one rdptr location filled RXRDY FIFO EMPTY rdptr 002aaa232 © ...
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... It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR[7]. 6.7 Sleep mode Sleep mode is an enhanced feature of the SC16C754B UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • ...
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... When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6]. 6.9 Programmable baud rate generator The SC16C754B UART contains a programmable baud generator that takes any clock input and divides divisor in the range between 1 and (2 divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 13 ...
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... Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Percent error difference between desired and actual 0.026 0.058 0.69 2.86 Percent error difference between desired and actual 0.026 0.034 0.312 0.628 1.23 © NXP B.V. 2008. All rights reserved. ...
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... Xoff1 word [2][4] 1 Xoff2 word 0 Transmission Control Register [2][5] (TCR) [2][5] 1 Trigger Level Register (TLR) [2][6] 1 FIFO ready register Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com XTAL1 XTAL2 1 1.8432 MHz 002aaa870 Write mode Transmit Holding Register (THR) Interrupt Enable Register (IER) FIFO Control Register (FCR) ...
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... NXP Semiconductors Table 10 lists and describes the SC16C754B internal registers. Table 10. SC16C754B internal registers Register Bit 7 [1] General register set RHR bit THR bit IER 0/CTS interrupt [2] enable FCR RX trigger level (MSB IIR ...
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... If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs. SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 9 for more register access information. Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...
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... FIFO. FIFO enable. logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Table 11 © NXP B.V. 2008. All rights reserved ...
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... Word length bits 1, 0. These two bits specify the word length to be transmitted or received. 00 — 5 bits 01 — 6 bits 10 — 7 bits 11 — 8 bits Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Table 12 © NXP B.V. 2008. All rights reserved ...
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... Data in receiver. logic data in receive FIFO (normal default condition) logic least one character in the RX FIFO Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...
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... MSR[4]. If auto-RTS is enabled, the RTS output is controlled by hardware flow control. MCR[0] DTR logic 0 = force DTR output to inactive (HIGH) logic 1 = force DTR output to active (LOW). In loopback mode, controls MSR[5]. Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...
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... DSR. Indicates that DSR input (or MCR[0] in loopback mode) has changed state. Cleared on a read. CTS. Indicates that CTS input (or MCR[1] in loopback mode) has changed state. Cleared on a read. Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com shows modem status register bit settings © NXP B.V. 2008. All rights reserved ...
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... THR interrupt Receive holding register interrupt. logic 0 = disable the RHR interrupt (normal default condition) logic 1 = enable the RHR interrupt Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Table 16 Section 6.7 “Sleep mode” for details. © NXP B.V. 2008. All rights reserved. ...
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... Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Table 18. 18. IIR[1] IIR[0] Source of the interrupt 1 0 Receiver line status error 0 0 Receiver time-out interrupt 0 0 RHR interrupt 1 0 THR interrupt 0 0 Modem interrupt ...
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... IER[7:4], FCR[5:4], and MCR[7:5] can be modified, that is, this bit is therefore a write enable. Combinations of software flow control can be selected by programming these bits. See Table 3 “Software flow control options Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Table 19 shows (EFR[3:0])”. © NXP B.V. 2008. All rights reserved. ...
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... TX trigger level number of spaces available in the TX FIFO 1 = there are at least a TX trigger level number of spaces available in the TX FIFO Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com shows transmission control register bit N , where N is the 4 © ...
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... MCR (04h), save in temp3 set MCR (04h) to 40h + temp3 set TCR (06h) to VALUE set MCR (04h) to temp3 set LCR (03h) to BFh set EFR (02h) to temp2 set LCR (03h) to temp1 Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...
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... EFR (02h) to 10h + temp2 set LCR (03h) to 00h read MCR (04)h, save in temp3 set MCR (04h) to temp3 + 80h set LCR (03)h to BFh set EFR (02h) to temp2 set LCR (03h) to temp1 Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com [1] EFh [1] 7Fh © NXP B.V. 2008. All rights reserved ...
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... V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Limiting values Parameter Conditions supply voltage voltage on any other pin any input only pin ambient temperature operating in free-air storage temperature Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Min Max Unit - 7 V GND 0 0.3 ...
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... V on non-hysteresis inputs. IH(max) Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com V = 3.3 V and Max Min Typ Max + ...
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... RCLK [ load - 100 - 100 8T 24T RCLK [3] [3] - 100 - 1T RCLK [3] - 100 - 100 - 8T RCLK [3] [4] 200 Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Min Max Min - ...
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... V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs t 6h valid address t 13h active t 15d t 13w active t 16h t 16s data t 6h valid address t 7h active active t t 12h 12d data Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com 002aaa109 002aaa110 © NXP B.V. 2008. All rights reserved ...
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... V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs t 17d change of state change of state t 18d active active w(clk) Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com change of state t 18d active active t 19d active active t 18d change of state 002aaa352 002aac357 © NXP B.V. 2008. All rights reserved. ...
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... data bits 6 data bits 7 data bits 16 baud rate clock start bit data bits ( Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com next data parity stop start bit bit bit 20d active t 21d active ...
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... data bits 6 data bits 7 data bits active transmitter ready t 22d t 23d 16 baud rate clock Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com parity stop bit bit first byte that reaches the trigger level t 25d active data ready t ...
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... data bits 6 data bits 7 data bits t 28d t 27d FIFO full Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com next data parity stop start bit bit bit ready 002aab062 parity stop bit bit ...
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... 2.5 scale (1) ( 0.20 7.1 7.1 9.15 9.15 0.4 0.09 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com detail (1) ( 0.75 0.64 0.64 1 0.2 0.08 0.08 0.45 0.36 0.36 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-20 © NXP B.V. 2008. All rights reserved. ...
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... scale (1) ( 0.18 12.1 12.1 14.15 14.15 0.5 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com detail (1) ( 0.75 1.45 1.45 1 0.2 0.15 0.1 0.30 1.05 1.05 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-25 © NXP B.V. 2008. All rights reserved. ...
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... 0.81 24.33 24.33 23.62 23.62 25.27 25.27 1.27 0.66 24.13 24.13 22.61 22.61 25.02 25.02 0.032 0.958 0.958 0.93 0.93 0.995 0.995 0.05 0.026 0.950 0.950 0.89 0.89 0.985 0.985 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com detail X ( max. max. 1.22 1.44 0.18 0.18 0.1 2.16 2.16 1.07 1 ...
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... Solder bath specifications, including temperature and impurities SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 28. Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Figure 28) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... Divisor Latch LSB Divisor Latch MSB Direct Memory Access First In, First Out Least Significant Bit Most Significant Bit Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com peak temperature time 001aac844 © NXP B.V. 2008. All rights reserved ...
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... Rdy)”, last paragraph: changed from “when any of the characteristics”: added Table note [4] Product data sheet Product data sheet Product data sheet Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com Change notice Supersedes - SC16C754B_3 Footnote 1 on page 1 and its reference at t RESET - SC16C754B_2 - SC16C754B_1 - - © NXP B.V. 2008. All rights reserved. . ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 04 — 6 October 2008 SC16C754B www.DataSheet4U.com © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SC16C754B www.DataSheet4U.com All rights reserved. Date of release: 6 October 2008 Document identifier: SC16C754B_4 ...