SC16C754B NXP Semiconductors, SC16C754B Datasheet - Page 18

• Manufacturer Part Number: SC16C754B
• Description: 5 V - 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.)
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C754B_4
Product data sheet
6.6.2.1 Transmitter
6.6.2.2 Receiver
6.6.2 Block DMA transfers (DMA mode 1)
6.7 Sleep mode
Figure 12
TXRDY is active when there is a trigger level number of spaces available. It becomes
inactive when the FIFO is full.
RXRDY becomes active when the trigger level has been reached, or when a time-out
interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is
flagged by LSR[7].
Sleep mode is an enhanced feature of the SC16C754B UART. It is enabled when EFR[4],
the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:
Remark: Sleep mode will not be entered if there is data in the RX FIFO.
In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced. The UART will
wake up when any change is detected on the RX line, when there is any change in the
state of the modem input pins, or if data is written to the TX FIFO.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
Fig 12. TXRDY and RXRDY in DMA mode 1
•
•
•
The serial data input line, RX, is idle (see
conditions”).
The TX FIFO and TX shift register are empty.
There are no interrupts pending except THR and time-out interrupts.
wrptr
trigger
wrptr
level
shows TXRDY and RXRDY in DMA mode 1.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
TX
Rev. 04 — 6 October 2008
FIFO full
TXRDY
TXRDY
Section 6.8 “Break and time-out
trigger
rdptr
rdptr
level
FIFO EMPTY
RX
SC16C754B
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© NXP B.V. 2008. All rights reserved.
RXRDY
RXRDY
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