CS8416-IS Cirrus Logic, CS8416-IS Datasheet - Page 36

• Manufacturer Part Number: CS8416-IS
• Description: 192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: Cirrus Logic

36
RST
AD0/CS
AD1/CDIN
SCL/CCLK
SDA/
CDOUT
AD2/GPO2
GPO1
GPO0
SDOUT
OLRCK
OSCLK
OMCK
RMCK
14
15
16
17
18
19
20
26
28
27
25
24
9
Reset ( Input ) - When RST is low, the CS8416 enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks
are stable in frequency and phase.
Address Bit 0 (I
CS8416 into SPI control port mode. With no falling edge, the CS8416 defaults to I
mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the
CS8416
Address Bit 1 (I
SPI mode, CDIN is the input data line for the control port interface
Control Port Clock ( Input ) - Serial control interface clock and is used to clock control data bits into and
out of the CS8416.
Serial Control Data I/O (I
line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the
output data from the control port interface on the CS8416
General Purpose Output 2 (Output) - If using the I
through a 47 k Ω resistor. See
General Purpose Output 1 (Output) See
General Purpose Output 0 (Output) See
Serial Audio Output Data ( Output ) - Audio data serial output pin. This pin must be pulled high to VL+
through a 47 K Ω resistor to place the part in Software Mode.
Serial Audio Output Left/Right Clock ( Input / Output ) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs)
Serial Audio Output Bit Clock ( Input / Output ) - Serial bit clock for audio data on the SDOUT pin
System Clock ( Input ) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the
Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as
reference signal for OMCK/RMCK ratio expressed in register 24
Input Section Recovered Master Clock ( Output ) - Input section recovered master clock output when
PLL is used. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x. It may also be
tri-stated by the RXD bit in the Control 4 register (04h).
2
2
C) / Serial Control Data in (SPI) ( Input ) - In I
C) / Control Port Chip Select (SPI) ( Input) - A falling edge on this pin puts the
2
C) / Data Out (SPI) ( Input/Output ) - In I
“General Purpose Outputs” on page 22
“General Purpose Outputs” on page 22
“General Purpose Outputs” on page 22
2
C control port, this pin must be pulled high or low
2
C mode, AD1 is a chip address pin. In
2
C mode, SDA is the control I/O data
for GPO functions.
2
for GPO functions.
C mode. In I
for GPO functions.
CS8416
DS578PP2
2
C