CS8416-IS Cirrus Logic, CS8416-IS Datasheet - Page 32

• Manufacturer Part Number: CS8416-IS
• Description: 192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: Cirrus Logic

8.13
8.14
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ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND
ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE
ABS FRAME
CONTROL
SECOND
MINUTE
FRAME
TRACK
INDEX
ZERO
7
0
7
Interrupt 1 Status (0Dh)
Q-Channel Subcode (0Eh - 17h)
PCCH – PC burst preamble change.
OSLIP - Serial audio output port data slip interrupt
DETC - D to E C-buffer transfer interrupt.
C_CHANGE -Indicates that the current 10 bytes of channel status is different from the previous
RERR - A receiver error has occurred.
QCH – A new block of Q-subcode is available for reading. The data must be read within 588 AES3
FCH – Format Change: Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once
since the register was last read. A “0” means the associated interrupt condition has NOT occurred
since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode
is set to level and the interrupt source is still true. Status bits that are masked off in the associated
mask register will always be “0” in this register.
Indicates that the PC byte has changed from its previous value. The user has TBD frames to read
new value before it can potentially be overwritten again. If the IEC61937 bit in the Format Detect Sta-
tus register goes high, it will cause a PCCH interrupt even if the PC byte hasn’t changed since the last
time the IEC61937 bit went high.
When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data
source, This bit will go high every time a data sample is dropped or repeated.
The source for this bit is true during the D to E buffer transfer in the C bit buffer management process.
The Receiver Error register may be read to determine the nature of the error which caused the inter-
rupt.
Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 0Eh is Q[0]
while bit 0 of address 0Eh is Q[7]. Similarly bit 0 of address 17h corresponds to Q[79].
10 bytes. (5 bytes per channel)
bits in the Format Detect Status register transition from 0 to 1. When these bits in the Format
Detect Status register transition from 1 to 0, an interrupt will not be generated.
frames after the interrupt occurs to avoid corruption of the data by the next block.
ABS FRAME
CONTROL
SECOND
MINUTE
TRACK
FRAME
INDEX
PCCH
ZERO
6
6
ABS FRAME
CONTROL
SECOND
MINUTE
FRAME
TRACK
OSLIP
INDEX
ZERO
5
5
ABS FRAME
CONTROL
SECOND
MINUTE
FRAME
TRACK
INDEX
ZERO
DETC
4
4
ABS FRAME
ADDRESS
SECOND
MINUTE
TRACK
FRAME
INDEX
ZERO
CCH
3
3
ABS FRAME
ADDRESS
SECOND
MINUTE
FRAME
TRACK
INDEX
RERR
ZERO
2
2
ABS FRAME
ADDRESS
SECOND
MINUTE
FRAME
TRACK
INDEX
ZERO
QCH
1
1
ABS FRAME
ADDRESS
SECOND
CS8416
MINUTE
TRACK
FRAME
INDEX
ZERO
DS578PP2
FCH
0
0