CS8416-IS Cirrus Logic, CS8416-IS Datasheet - Page 16

• Manufacturer Part Number: CS8416-IS
• Description: 192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
• Manufacturer: Cirrus Logic

5 S/PDIF RECEIVER
The CS8416 includes an AES3/SPDIF digital au-
dio receiver. The AES3 receiver accepts and de-
codes audio and digital data according to the AES3,
IEC60958 (S/PDIF), and EIAJ CP-1201 interface
standards. The receiver consists of an analog differ-
ential input stage, driven through analog input pins
RXP0 to RXP7 and a common RXN, a PLL based
clock recovery circuit, and a decoder which sepa-
rates the audio data from the channel status and
user data.
Software Mode
The first 5 bytes of both channels status block is
stored in dedicated registers. Channel A status data
is stored in control port registers 19h to 1Dh. Chan-
nel B status data is stored in control port registers
1Eh to 22h.
Q Subcode data is stored in control port registers
0Eh to 17h.
PC Burst preamble is stored in control port regis-
ters 23h and 24h. PD Burst preamble is stored in
control port registers 25h and 26h.
U and C data may be selected for output on GPO
pins.
External components are used to terminate and iso-
late the incoming data cables from the CS8416.
These components are detailed in Appendix A.
Hardware Mode
U and C bits are output on pins 18 and 19 respec-
tively. See Section
lection” on page 40
(Defaults & Controls)” on page 40
these pins.
5.1
The CS8416 employs a 8:2 S/PDIF input multi-
plexer to accommodate up to eight channels of in-
put digital audio data. Digital audio data may be
single- ended or differential. Differential inputs uti-
lize RXP[0-7] and a shared RXN. Single ended sig-
16
8:2 S/PDIF Input Multiplexer
“Hardware Mode Function Se-
and
“Hardware Mode Settings
to configure
nals are accommodated by using RXP inputs and
AC coupling RXN to ground.
All inputs to the CS8416 8:2 input multiplexer
should be coupled through a capacitor. The recom-
mended capacitor value is 0.01uF to 0.1uF. The
recommended dielectrics are COG or X7R.
Software Mode
The multiplexer select line control is accessed
through bits RXSEL[2:0] in control port register 4.
The multiplexer defaults to RXP0.
The second output of the input multiplexer is used
to provide the selected input as a source to be out-
put on a GPO pin via the internal TX pin. This pass
through signal is selected by TXSEL[2:0] in con-
trol port register 04h. The single-ended signal is re-
solved to full-rail, but is not de-jittered before it is
output.
Hardware Mode
In hardware mode the input to the decoder is select-
ed by dedicated pins, RXSEL[1:0].
The pass through signal is selected by dedicated
pins, TXSEL[1:0] for output on the dedicated TX
pin.
Selectable inputs are restricted to RXP0 to RXP3
for both the receiver and the TX output pin. These
inputs are selected by RXSEL[1:0] and TX-
SEL[1:0] respectively.
General
Unused multiplexer inputs should be left floating
or grounded.
The input voltage range for the input multiplexer is
set by the I/O power supply pin, VL+. The input
voltage of the RXP and RXN pins is also set by the
level of VL+.
5.2
An on-chip Phase Locked Loop (PLL) is used to re-
cover the clock from the incoming data stream.
PLL, Jitter Attenuation, and Clock
Switching
CS8416
DS578PP2