CS8405A Cirrus Logic, CS8405A Datasheet - Page 23

• Manufacturer Part Number: CS8405A
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: Cirrus Logic

8.13
8.14
Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block
mode) is accessible through these register addresses.
8.15
DS469PP4
ID3
7
0
7
User Data Buffer Control (13h)
Channel Status bit or User bit Data Buffer (20h - 37h)
CS8405A I.D. and Version Register (7Fh) (Read Only)
UD - User bit data pin (U) direction specifier
UBM1:0 - Sets the operating mode of the AES3 User bit manager
EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only).
ID3:0 - ID code for the CS8405A. Permanently set to 0110
VER3:0 - CS8405A revision level. Revision A is coded as 0001
Default = ‘0’
0 - The U pin is an input. The User bit data is latched in on both rising and falling edges of
1 - The U pin is an output. The received U data is clocked out on both rising and falling edges
Default = ‘00’
00 - Transmit all zeros mode
01 - Block mode
10 - Reserved
11 - Reserved
Default = ‘0’
0 - Allow U-data E to F buffer transfers
1 - Inhibit U-data E to F buffer transfer
OLRCK. This setting also chooses the U pin as the source for transmitted U data.
of ILRCK. This setting also chooses the U data buffer as the source of transmitted U data.
ID2
6
0
6
ID1
5
0
5
ID0
UD
4
4
UBM1
VER3
3
3
UBM0
VER2
2
2
VER1
1
1
0
CS8405A
EFTUI
VER0
0
0
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