SSD1322 SOLOMON SYSTECH, SSD1322 Datasheet - Page 43

• Manufacturer Part Number: SSD1322
• Description: Dot Matrix High Power OLED/PLED Segment/Common Driver
• Manufacturer: SOLOMON SYSTECH

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10.1.10Enable Partial Display (A8h)
The partial mode display area is defined this triple byte command.
the partial mode display with start row address A[6:0] = 20h and end start row address B[6:0] = 5Fh at MUX
ratio = 128.
10.1.11Exit Partial Display (A9h)
This single byte command is sent to exit the partial mode display area (command A8h).
10.1.12Set Function selection (ABh)
This double byte command is used to enable or disable the VDD regulator.
Internal VDD regulator is selected when the bit A[0] is set to 0b, while external VDD is selected when A[0] is
set to 1b.
10.1.13 Set Display ON/OFF (AEh / AFh)
These single byte commands are used to turn the OLED panel display ON or OFF.
When the display is ON (command AFh), the selected circuits by Set Master Configuration command will be
turned ON. When the display is OFF (command AEh), those circuits will be turned off, the segment is in V
state and common is in high impedance state.
10.1.14 Set Phase Length (B1h)
This double byte command sets the length of phase 1 and 2 of segment waveform of the driver.
10.1.15 Set Front Clock Divider / Oscillator Frequency (B3h)
This double byte command consists of two functions:
10.1.16 Set GPIO (B5h)
This double byte command is used to set the states of GPIO0 and GPIO1 pins. Refer to
SSD1322
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Phase 1 (A[3:0]): Set the period from 5 to 31 in the unit of 2 DCLKs. A larger capacitance of the
OLED pixel may require longer period to discharge the previous data charge completely.
Phase 2 (A[7:4]): Set the period from 3 to 15 in the unit of DCLKs. A longer period is needed to
charge up a larger capacitance of the OLED pixel to the target voltage V
Front Clock Divide Ratio (A[3:0])
Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16,
with reset value = 1. Please refer to Section 8.5 for the detail relationship of DCLK and CLK.
Oscillator Frequency (A[7:4])
Program the oscillator frequency Fosc which is the source of CLK if CLS pin is pulled HIGH. The 4-
bit value results in 16 different frequency settings being available.
Rev 0.10
P 43/56 Apr 2008
Figure 10-14 : Example of Partial Mode Display
GDDRAM
Display
Figure 10-14
shows an example of enabling
P
.
Table 9-1
Solomon Systech
for details.
SS
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