SSD1322 SOLOMON SYSTECH, SSD1322 Datasheet - Page 21

• Manufacturer Part Number: SSD1322
• Description: Dot Matrix High Power OLED/PLED Segment/Common Driver
• Manufacturer: SOLOMON SYSTECH

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COM126
COM127
COM
Outputs
8.2
When RES# input is pulled LOW, the chip is initialized with the following status:
8.3
8.3.1 GDDRAM structure in Gray Scale mode
The GDDRAM address map in Table 8-6 shows the GDDRAM in Gray Scale mode. Since in Gray Scale
mode, there are 16 gray levels. Therefore four bits (one nibble) are allocated for each pixel. For example
D30480[3:0] in Table 8-6 corresponds to the pixel located in (COM127, SEG2). So the lower nibble and
higher nibble of D0, D1, D2, …, D30717, D30718, D30719 in Table 8-6 represent the 480x128 data nibbles
in the GDDRAM.
8.3.2 Data bus to RAM mapping
COM0
COM1
SSD1322
|
1. Display is OFF
2. 128 MUX Display Mode
3. Normal segment and display data column address and row address mapping (SEG0 mapped to
4. Display start line is set at display RAM address 0
5. Column address counter is set at 0
6. Normal scan direction of the COM outputs
7. Contrast control register is set at 7Fh
Reset Circuit
GDDRAM
RAM
Row
Address
(HEX)
address 00h and COM0 mapped to address 00h)
7E
7F
00
01
|
D30241[3:0] D30241[7:4] D30240[3:0] D30240[7:4]
D30481[3:0] D30481[7:4] D30480[3:0] D30480[7:4]
D241[3:0]
D1[3:0]
SEG0
Bus width
Rev 0.10
8 bits
Read / Write Data
00
D241[7:4]
P 21/56 Apr 2008
D1[7:4]
SEG1
Table 8-6 : GDDRAM in Gray Scale mode (RESET)
Input order
2
1
nd
st
D240[3:0]
D0[3:0]
SEG2
Table 8-7 : Data bus usage
00
D7
3
1
D240[7:4]
D0[7:4]
SEG3
Corresponding to one pixel
D6
3
1
D5
|
3
1
D30479[3:0]D30479[7:4]D30478[3:0] D30478[7:4]
D30719[3:0]D30719[7:4]D30718[3:0] D30718[7:4]
D239[3:0]
D479[3:0]
Data bus D[7:0]
SEG476
D4
3
1
Corresponding to one pixel
77
D3
D239[7:4]
D479[7:4]
2
0
SEG477
D2
2
0
D238[3:0]
D478[3:0]
SEG478
D1
2
0
D0
2
0
77
D238[7:4]
D478[7:4]
SEG479
Solomon Systech
SEG
Outputs
RAM
Column
address
(HEX)
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