AN2536 Freescale Semiconductor / Motorola, AN2536 Datasheet - Page 6

• Manufacturer Part Number: AN2536
• Description: MC9328MX1 and MC9328MXL High Speed Layout Design Guidelines
• Manufacturer: Freescale Semiconductor / Motorola

Design Consideration
2.2 On-Board Noise Source
Crosstalk
Crosstalk is the unwanted coupling of signals between parallel traces. Proper routing and layer stack-up
through microstrip and stripline layouts can minimize crosstalk.
To reduce crosstalk in dual-stripline layouts, which have two signal layers next to each other, route all
traces perpendicular, increase the distance between the two signal layers, and minimize the distance
between the signal layer and adjacent plane.
Use the following steps to reduces crosstalk in either microstrip or stripline layouts:
Crosstalk also increases when two or more single-ended traces run parallel and are not spaced far enough
apart. The distance between the centers of two adjacent traces should be at least four times the trace width.
To improve design performance, lower the distance between the trace and the ground plane to under
10 mils without changing the separation between two traces.
Signal Integrity
For a single-ended trace, like clock transmission line, it could be improved using the following guidelines:
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Figure 8. Propagation Delay vs. Dielectric Constant For Microstrip and Stripline Traces.
Widen spacing between signal lines as much as routing restrictions will allow. Try not to bring
traces closer than three times the dielectric height.
Design the transmission line so that the conductor is as close to the ground plane as possible. This
technique will couple the transmission line tightly to the ground plane and help decouple it from
adjacent signals.
Use differential routing techniques where possible, especially for critical nets (i.e., match the
lengths as well as the gyrations that each trace goes through).
If there is significant coupling, route single-ended signals on different layers orthogonal to each
other.
Minimize parallel run lengths between single-ended signals. Route with short parallel sections and
minimize long, coupled sections between nets.
Keep clock traces as straight as possible. Use arc-shaped traces instead of right-angle bends.
Do not use multiple signal layers for clock signals.
Do not use via in clock transmission lines. Via can cause impedance change and reflection.
Freescale Semiconductor, Inc.
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MC9328MX1/MXL Application Note
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MOTOROLA