AN2536 Freescale Semiconductor / Motorola, AN2536 Datasheet - Page 19

• Manufacturer Part Number: AN2536
• Description: MC9328MX1 and MC9328MXL High Speed Layout Design Guidelines
• Manufacturer: Freescale Semiconductor / Motorola

The PCB design were:
Based on the current layout and component capacitive loading, we have:
MC9328MX1 Demo v0.1 (PDA Form Factor Design) successfully achieves 96 MHz at both 3.0V and
1.8V memory bus voltages, up to 80deg. To qualify the system stability, standard “bit-walk” memory tests
were conducted on both a standalone (lightly loaded) and Linux OS (heavy loaded) environment from
selected samples in each of the process corners (refer to Section 5, “References,” for details). Section 5
also provides the details of the selected sample for this qualification test. Finally, please refer to Section 4,
“Design Guidelines on PCB,” for a summary of recommended guidelines for designing a high speed low
power PCB using the MC9328MX1/MXL.
4 Design Guidelines on PCB
The following recommendations are for designing high-speed low-power PCB for MC9328MX1/MXL
silicon:
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8-layer (refer to Figure 25 on page 17)
ε
Copper Trace width = 6 mil (rings are not added in the inter-layer of the vias)
Via Size = 20mil (10mil drill hole SDRAM each)
(The form factor has two x16 SDRAMs and one x32 Flash - DOC)
For SDCLK < (route:5pF + chip:[4+4+4.7]=12.7pF) = 17.7pF
For Address < (route:15pF + chip:[4+4+6.5]=14.5pF) = 29.5pF
For Data < (route: 7pF + chip:[6+6.5]=12.5pF) = 19.5pF
For Control < (route: 5.5pF + chip:[4+4+4.7]=12.7pF) = 18.2pF
Widen spacing between signal lines as much as routing restrictions will allow. Try not to bring
traces closer than three times the dielectric height.
Design the transmission line so that the conductor is as close to the ground plane as possible. This
technique will couple the transmission line tightly to the ground plane and help decouple it from
adjacent signals.
Use differential routing techniques where possible, especially for critical nets (i.e., match the
lengths as well as the gyrations that each trace goes through).
If there is significant coupling, route single-ended signals on different layers orthogonal to each
other.
Minimize parallel run lengths between single-ended signals. Route with short parallel sections and
minimize long, coupled sections between nets.
Keep clock traces as straight as possible. Use arc-shaped traces instead of right-angle bends.
Do not use multiple signal layers for clock signals.
Do not use via in clock transmission lines. Via can cause impedance change and reflection.
Place a ground plane next to the outer layer to minimize noise. If you use an inner layer to route the
clock trace, sandwich the layer between reference planes.
Terminate clock signals to minimize reflection.
Use point-to-point clock traces as much as possible.
r
for FR-4 is 4.1
Freescale Semiconductor, Inc.
For More Information On This Product,
MC9328MX1/MXL Application Note
Go to: www.freescale.com
Design Guidelines on PCB
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