AN2536 Freescale Semiconductor / Motorola, AN2536 Datasheet - Page 10

• Manufacturer Part Number: AN2536
• Description: MC9328MX1 and MC9328MXL High Speed Layout Design Guidelines
• Manufacturer: Freescale Semiconductor / Motorola

Design Consideration
Analyzing Ground Bounce—Figure 14, shows a simple model for analyzing ground bounce. The external
components driven by the device appear as capacitance loads to that device (C1 to Cn). These capacitive
loads store a charge determined by the following equation:
Thus, the charge increases as the voltage and/or load capacitance increase. A device’s environment and
ground path have intrinsic inductances (shown in the above diagram as L1, L2, and L3). L1 is the
inductance of the bond wire from the device’s die to its package pin, and of the pin itself. L2 is the
inductance of the connection mechanism between the device’s ground pin and the PCB. This inductance is
greatest when the device is connected to the PCB through a socket. L3 is the inductance of the PCB trace
between the device and the PCB location where the power supply’s reference ground is connected.
Ground bounce occurs when multiple outputs switch from high to low. The transition causes the charge
stored in the load capacitances to flow into the device. The sudden rush of current (di/dt) exits the device
through the inductances (L) to board ground, generating a voltage (V) determined by the equation V = L
(di/dt). This voltage difference between board ground and device ground causes the relative ground level
for low or quiet outputs to temporarily rise or bounce. Although the rush of current is brief, the magnitude
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Eliminate pull-up resistors or use pull-down resistors.
Use multi-layer PCBs that provide separate VCC and ground planes to utilize the intrinsic
capacitance of GND-VCC plane.
Add 10 to 30 ohm resistors in series to each of the switching outputs to limit the current flow into
each of the outputs.
Create synchronous designs that will not be affected by momentarily switching pins.
Assign I/O pins to minimize local bunching of output pins.
Place the power and ground pins next to each other. The total inductance will be reduced by mutual
inductance, since current flows in opposite directions in power and ground pins.
Use a bigger via size to connect the capacitor pad to the power and ground plane to minimize the
inductance in decoupling capacitors.
Use surface mount capacitors to minimize the lead inductance.
Use low effective series resistance (ESR) capacitors. The ESR should be < 400 m ohm.
Each GND pin/via should be connected to the ground plane individually.
To add extra capacitance on the board, It is recommended to place a ground plane next to each power
(VCC) plane. This placement gives zero lead inductance and no ESR. The dielectric thickness
between the two planes should be ~5 mils.
Figure 14. Simple Model for Analyzing Ground Bounce
Charge (Q) = [voltage (V) capacitance (C)]
Freescale Semiconductor, Inc.
For More Information On This Product,
MC9328MX1/MXL Application Note
Go to: www.freescale.com
MOTOROLA
Eqn. 9