CY25568 Cypress Semiconductor, CY25568 Datasheet - Page 6

• Manufacturer Part Number: CY25568
• Description: Spread Spectrum Clock Generator
• Manufacturer: Cypress Semiconductor

Spread % Selection
The CY25568 provides Center-Spread, Down-Spread and No-Spread functions. These functions and the amount of Spread% are
selected by using 3-Level S0 and S1 digital inputs and are given in
Table 3. Spread% Selection
3-Level Digital Inputs
S0, S1, D0, D1, and FRSEL digital inputs of the CY25568 are designed to sense 3 different logic levels designated as High - 1,
Low- 0 and Middle- M. With this 3-Level digital input logic, the CY25568 is able to detect 9 different logic states in the case of (S0,
S1) and (D0, D1) logic pairs and 3 different logic states in the case of FRSEL.
S0, S1, D0, D1, and FRSEL pins include an on chip 20K (10K /10K) resistor divider. No external application resistors are needed to
implement the 3-Level logic levels as shown in the following:
Logic State 0 = 3-Level logic pin connected to GND.
Logic State M = 3-Level logic pin left floating (no connection).
Logic State 1 = 3-Level logic pin connected to VDD.
Figure 2
Document Number: 38-07111 Rev. *D
(MHz)
10-12
12-14
14-16
16-20
20-24
24-28
28-32
8-10
XIN
4-5
5-6
6-7
7-8
illustrates how to implement 3-Level Logic.
FRSEL
M
M
M
M
0
0
0
0
1
1
1
1
CENTER
+/–1.4
+/–1.3
+/–1.2
+/–1.1
+/–1.4
+/–1.3
+/–1.2
+/–1.1
+/–1.4
+/–1.3
+/–1.2
+/–1.1
S1=0
S0=0
(%)
DO, D1, S0, S1
to GND
FRSEL
and
CENTER
LOW (0)
+/–1.2
+/–1.1
+/–0.9
+/–0.9
+/–1.2
+/–1.1
+/–0.9
+/–0.9
+/–1.2
+/–1.1
+/–0.9
+/–0.9
S0=M
LOGIC
S1=0
(%)
GND
CENTER
+/–0.6
+/–0.5
+/–0.5
+/–0.4
+/–0.6
+/–0.5
+/–0.5
+/–0.4
+/–0.6
+/–0.5
+/–0.5
+/–0.4
S1=0
S0=1
(%)
UNCONNECTED
D0, D1, S0, S1
Figure 2. 3-Level Logic
FRSEL
MIDDLE (M)
and
CENTER
LOGIC
+/–0.5
+/–0.4
+/–0.4
+/–0.3
+/–0.5
+/–0.4
+/–0.4
+/–0.3
+/–0.5
+/–0.4
+/–0.4
+/–0.3
S1=M
S0=0
(%)
Table
3.
DOWN
S1=1
S0=1
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
(%)
D0, D1, S0, S1
FRSEL
to VDD
and
DOWN
S1=1
S0=0
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
HIGH (H)
(%)
LOGIC
VDD
DOWN
S1=M
S0=1
–1.9
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
(%)
–.7
DOWN
S0=M
S1=1
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
(%)
CY25568
Page 6 of 14
SPREAD
S1=M
S0=M
NO
0
0
0
0
0
0
0
0
0
0
0
0