CY25568 Cypress Semiconductor, CY25568 Datasheet
CY25568
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CY25568 Summary of contents
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... REFERENCE DIVIDER MODULATION CONTROL INPUT DECODER LOGIC PD# FRSEL • 198 Champion Court • San Jose CY25568 7 REFOUT PD and CP LF VCO VCO COUNTER SSCLK1 6 DIVIDER and SSCLK2 9 MUX 8 SSCLK3 , CA 95134-1709 • 408-943-2600 Revised July 18, 2011 ...
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... Modulation Rate .......................................................... 6 Document Number: 38-07111 Rev. *D Characteristic Curves ...................................................... 7 SSCG Profiles ............................................................. 8 Application Schematic ..................................................... 9 Ordering Code Definitions ........................................... 9 Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 CY25568 Page ...
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... This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The CY25568 input frequency range MHz and accepts clock, crystal, and ceramic resonator inputs. The output clocks can be programmed to produce 1x, 2x, and 4x multiplication of Document Number: 38-07111 Rev ...
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... CY25568 Conditions V V S0,S1,D0,D1 and FRSEL Inputs V S0,S1,D0,D1 and FRSEL Inputs V S0,S1,D0,D1 and FRSEL Inputs V PD# input only V PD# input only V IOH = 4 ma, all output clocks V IOH = 6 ma, all output clocks V IOL = 4 ma, all output clocks V IOL = 10 ma, all output clocks ...
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... V, T=25 C, CL=15pF. Rise/Fall time at 0.4 and 2.4 V, duty cycle at 1 CCJ3 Cycle-to-cycle jitter Input Frequency Range and Selection The CY25568 input frequency range MHz. This range is divided into 3 segments and controlled by 3-Level FRSEL pin as given in Table 1. Table 1. Input Frequency Selection ...
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... S0, S1, D0, D1, and FRSEL digital inputs of the CY25568 are designed to sense 3 different logic levels designated as High - 1, Low- 0 and Middle- M. With this 3-Level digital input logic, the CY25568 is able to detect 9 different logic states in the case of (S0, S1) and (D0, D1) logic pairs and 3 different logic states in the case of FRSEL. ...
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... Power-down (PD#) CY25568 includes a Power-down (PD#, Pin 10) function. This input uses standard 2-Level CMOS logic and is internally pulled up to VDD (HIGH). Connect this pin to GND if power turned off. Modulation Rate Spread Spectrum Clock Generators use frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies ...
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... Characteristic Curves The following curves demonstrate the characteristic behavior of the CY25568 when tested over a number of environmental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in tables “DC Electrical Characteristics” on page 4 and Figure 3. Jitter vs. Input Frequency (No Load) ...
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... SSCG Profiles The CY25568 uses a non-linear frequency profile as shown in maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems. Figure 7. Spread Spectrum Profiles (Frequency versus Time) Xin = 6.0 MHz S1 Xin = 12.0 MHz S1 Document Number: 38-07111 Rev ...
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... Document Number: 38-07111 Rev. *D Figure 8. Application Schematic Package 16 Pin SOIC 16 Pin SOIC – Tape and Reel T = Tape and Reel; blank = Tube Temperature Range Commercial Pb-free Package 16-pin SOIC Base part number Company ID Cypress CY25568 Operating Temperature Range C Page ...
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... Package Diagram Document Number: 38-07111 Rev. *D Figure 9. 16-Pin (150-Mil) SOIC CY25568 51-85068 *C Page ...
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... VCD video compact disc WAN wide area network Document Conventions Units of Measure Symbol Unit of Measure % percent °C degree Celsius dB decibel mA milliamperes MHz Megahertz mm millimeter ms milliseconds mW milliwatts ns nanoseconds pF picofarad ps picoseconds V volts ohms W watts Document Number: 38-07111 Rev. *D CY25568 Page ...
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... Document History Page Document Title: CY25568 Spread Spectrum Clock Generator Document Number: 38-07111 Orig. of Rev. ECN Change ** 107515 NDP *A 108182 NDP *B 122682 RBI *C 2658020 KVM/PYRS *D 3319217 BASH Document Number: 38-07111 Rev. *D Submission Date 06/14/01 Convert from IMI to Cypress 07/03/01 Delete “Junction Temp” in Absolute maximum Ratings (page 4) 12/21/02 Added power-up requirements to Absolute Maximum Ratings information ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07111 Rev. *D cypress.com/go/plc cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB Revised July 18, 2011 CY25568 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...