IDT72V241L10PF IDT, Integrated Device Technology Inc, IDT72V241L10PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V241L10PF
• Description: IC FIFO SYNC 4KX9 10NS 32QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V241L10PF

• Function: Synchronous
• Memory Size: 36K (4K x 9)
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Configuration: Dual
• Density: 36Kb
• Access Time (max): 6.5ns
• Word Size: 9b
• Organization: 4Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 20mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V241L10PF; 800-1518

PIN CONFIGURATION
PIN DESCRIPTIONS
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
D
RS
WCLK
WEN1
WEN2/
Q
RCLK
REN1
REN2
OE
EF
PAE
PAF
FF
V
GND
Symbol
CC
0
0
-D
-Q
8
8
REN1
RCLK
REN2
PAE
GND
PAF
LD
INDEX
D
D
0
1
Data Inputs
Reset
Write Clock
Write Enable 1
Write Enable 2/
Load
Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
1
2
3
4
5
6
7
8
Name
32 31 30
9 10 11 12 13 14 15
TQFP (PR32-1, order code: PF)
29 28
TOP VIEW
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
27 26 25
Data inputs for a 9-bit bus.
When
and
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
If the FIFO is configured to have programmable flags,
LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to
have two write enables,
will not be written into the FIFO if the
The FIFO is configured at Reset to have either two write enables or programmable flags. If WEN2/
is HIGH at Reset, this pin operates as a second write enable. If WEN2/
as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write
enables,
into the FIFO if the
write or read the programmable flag offsets.
Data outputs for a 9-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
When
will not be read from the FIFO if the
When
Data will not be read from the FIFO if the
When
state.
When
HIGH, the FIFO is not empty.
When
offset at reset is Empty+7.
When
offset at reset is Full-7.
When
is not full.
One 3.3V volt power supply pin.
One 0 volt ground pin.
PAF
16
PAE
PAF
RS
REN1
REN1
OE
EF
FF
go HIGH, and
WEN1
is LOW, the FIFO is full and further data writes into the input are inhibited. When
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
FF
is set LOW, internal read and write pointers are set to the first location of the RAM array,
is LOW, the data output bus is active. If
24
23
22
21
20
19
18
17
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
and
and
is synchronized to WCLK.
4092 drw02
must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written
REN2
REN2
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
FF
CC
8
7
6
5
is LOW. If the FIFO is configured to have programmable flags, WEN2/
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
PAF
PAE
WEN1
PAE
is synchronized to WCLK.
and
EF
must be LOW and WEN2 must be HIGH to write data into the FIFO. Data
is synchronized to RCLK.
EF
is synchronized to RCLK.
2
EF
go LOW. A Reset is required before an initial Write after power-up.
FF
is LOW.
is LOW.
EF
is LOW.
COMMERCIAL AND INDUSTRIAL
REN1
RCLK
REN2
INDEX
GND
Description
PAE
PAF
OE
OE
D
D
1
0
is HIGH, the output data bus will be in a high-impedance
WEN1
TEMPERATURE RANGES
5
6
7
8
9
10
11
12
13
is the only Write Enable pin. When
PLCC (J32-1, order code: J)
14 15 16 17 18 19 20
4
3
2
TOP VIEW
LD
REN1
is LOW at Reset, this pin operates
1
COMMERCIAL AND INDUSTRIAL
32 31 30
and
TEMPERATURE RANGES
REN2
29
28
27
26
25
24
23
22
21
OCTOBER 22, 2008
FF
are asserted.
LD
is HIGH, the FIFO
4092 drw02a
is held LOW to
WEN1
EF
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
CC
8
7
6
5
FF
LD
is
is