IDT72V241L10PF IDT, Integrated Device Technology Inc, IDT72V241L10PF Datasheet - Page 11

• Manufacturer Part Number: IDT72V241L10PF
• Description: IC FIFO SYNC 4KX9 10NS 32QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V241L10PF

• Function: Synchronous
• Memory Size: 36K (4K x 9)
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Configuration: Dual
• Density: 36Kb
• Access Time (max): 6.5ns
• Word Size: 9b
• Organization: 4Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 20mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V241L10PF; 800-1518

NOTES:
1. m = PAF offset.
2. 256 - m words in FIFO for IDT72V201, 512 - m words for IDT72V211, 1,024 - m words for IDT72V221, 2,048 - m words for IDT72V231, 4,096 - m words for IDT72V241, 8,192 - m
3. t
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
(If Applicable)
NOTES:
1. n = PAE offset.
2. t
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
(If Applicable)
words for IDT72V251.
the rising edge of WCLK is less than t
SKEW2
the rising edge of RCLK is less than t
SKEW2
WCLK
WEN2
WEN1
REN2
RCLK
REN1,
WCLK
WEN1
WEN2
REN2
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
RCLK
REN1,
is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and
PAE
PAF
t
t
CLKH
CLKH
n words in FIFO
SKEW2
SKEW2
Full - (m + 1) words in FIFO
t
SKEW2
t
t
t
t
, then PAF may not change state until the next WCLK rising edge.
ENS
ENS
ENS
ENS
, then PAE may not change state until the next RCLK rising edge.
t
CLKL
t
CLKL
(2)
(1)
Figure 11. Programmable Empty Flag Timing
Figure 10. Programmable Full Flag Timing
t
t
ENH
ENH
t
t
ENH
ENH
t
PAE
(1)
(4)
11
t
PAF
t
ENS
t
n + 1 words in FIFO
Full - m words in FIFO
ENS
t
SKEW2
COMMERCIAL AND INDUSTRIAL
t
ENH
t
ENH
(3)
(2)
TEMPERATURE RANGES
(3)
t
OCTOBER 22, 2008
PAF
t
PAE
4092 drw12
4092 drw13