TMP86FS49AFG Toshiba Semiconductor, TMP86FS49AFG Datasheet - Page 54

• Manufacturer Part Number: TMP86FS49AFG
• Description: 8-Bit Microcontroller
• Manufacturer: Toshiba Semiconductor

3.2 Interrupt enable register (EIR)
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Interrupt Enable Registers
Interrupt Latches
(003BH, 003AH)
(003DH, 003CH)
EIRH,EIRL
(002CH)
(002EH)
ILH,ILL
EIRE
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Note 1: *: Don’t care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
ILE
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter-
rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe-
cuted before setting IMF="1".
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter-
rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe-
cuted before setting IMF="1".
EF15
IL15
15
15
EF23 to EF4
EF14
IL14
IL23 to IL2
14
14
IMF
EF13
IL13
13
13
EIRH (003BH)
EF12
IL12
ILH (003DH)
12
12
Individual-interrupt enable flag
(Specified for each bit)
Interrupt master enable flag
Interrupt latches
EF11
IL11
11
11
EF10
IL10
10
10
Page 38
EF9
IL9
9
9
EF8
0: No interrupt request
1: Interrupt request
IL8
8
8
0:
1:
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Disables the acceptance of all maskable interrupts
Enables the acceptance of all maskable interrupts
EF23
IL23
EF7
IL7
7
7
7
7
at RD
EF22
IL22
EF6
IL6
6
6
6
6
EF21
IL21
EF5
IL5
5
5
5
5
0: Clears the interrupt request
1: (Interrupt latch is not set.)
EIRE (002CH)
EIRL (003AH)
EF20
IL20
ILL (003CH)
ILE (002EH)
EF4
IL4
4
4
4
4
(Initial value: 00000000 000000**)
(Initial value: 00000000 0000***0)
EF19
IL19
at WR
IL3
3
3
3
3
(Initial value: 00000000)
(Initial value: 00000000)
EF18
IL18
IL2
TMP86FS49AFG
2
2
2
2
EF17
IL17
1
1
1
1
EF16
IL16
IMF
0
0
R/W
R/W
0
0