STA027 ST Microelectronics, STA027 Datasheet - Page 28

• Manufacturer Part Number: STA027
• Description: SBC Codec
• Manufacturer: ST Microelectronics

5 Register description
5.7
5.7.1
5.7.2
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Table 16.
SDI_CONFIGURATION registers description
POL_REQ :
Address : 0x59 (89)
Type : WO - DEC
Software Reset : 0
Description :
This register manage the polarity of the data REQ signal DREQ of the BS input interface.
If set to 0, data are requested when REQ = 0.
If set to 1, data are requested when REQ = 1.
INPUT_CONF :
Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
Description :
If set to 1 enable the configurability of the BSB input interfaces in burst mode thanks to following
register, else disable this configurability and take embedded default configuration.
Note that this embedded default configuration can be retrieved by user thanks to following
setting :
b7
b7
–
LR[15:10]
Bit fields
LR[4:0]
LR[9:5]
I_AUDIO_CONFIG1 = b00000000;// polarity choice
b6
b6
Position of the data within the LRCK phase :
Note:
Length-1 of the data.
Max value is 31.
Reserved : to be set to 0
- if CF1 = 0 (LSB), value must be set to[31 - SL[9:5] - bit position of the first bit
of data within the LRCK phase].
- if CF1 = 1 (MSB), value must be set to bit position of the first bit of data within
the LRCK phase.
b5
b5
that range of value for this bit position is [0:31].
CD00066274
b4
b4
b3
b3
Comment
b2
b2
b1
b1
STA027
b0
b0