STA027 ST Microelectronics, STA027 Datasheet - Page 16

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STA027

Manufacturer Part Number
STA027
Description
SBC Codec
Manufacturer
ST Microelectronics
Datasheet

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5 Register description
5.2.4
5.2.5
16/44
Description :
This register must contain a NDIV value that enables the audio PLL to generate a frequency of
ofact*192 kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
PLL_AUDIO_XDIV_192 :
Address : 0xDF (223)
Type : RW - DEC
Software Reset : 3
Description :
This register must contain a XDIV value that enables the audio PLL to generate a frequency of
ofact*192 kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
PLL_AUDIO_MDIV_192 :
Address : 0xE0 (224)
Type : RW - DEC
Software Reset : 12
Description :
This register must contain a MDIV value that enables the audio PLL to generate a frequency of
ofact*192 kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
b7
b7
ofact == 256
external crystal provide a CRYCK running at 14.31818 MHz
ofact == 256
external crystal provide a CRYCK running at 14.31818 MHz
ofact == 256
external crystal provide a CRYCK running at 14.31818 MHz
b6
b6
b5
b5
CD00066274
b4
b4
b3
b3
b2
b2
b1
b1
STA027
b0
b0

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