MACH445-12 Lattice, MACH445-12 Datasheet - Page 15

• Manufacturer Part Number: MACH445-12
• Description: High-Density EE CMOS Programmable Logic
• Manufacturer: Lattice

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
Input Register with Standard-Hold-Time Option
Parameter
Symbol
f
t
t
t
t
t
t
t
MAXIR
t
t
t
t
t
t
WICH
t
t
t
WICL
WIGL
t
t
PDLL
IGOL
IGSA
IGSS
ARW
t
t
SLLA
SLLS
t
ARR
t
APW
t
t
APR
PDL
IGO
HIR
ICS
SIR
HIL
AR
AP
EA
ER
SIL
Input Register Clock Width
Parameter Description
Input Register Clock to Output Register Setup
Maximum Input Register Frequency
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent
Output Latch
Input Latch Gate to Output Latch Setup Using
Product Term Output Latch Gate
Input Latch Gate to Output Latch Setup Using Global
Output Latch Gate
Input Latch Gate Width LOW
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 3)
Asynchronous Reset Recovery Time (Note 3)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 3)
Asynchronous Preset Recovery Time (Note 3)
Input, I/O, or Feedback to Output Enable (Note 2)
Input, I/O, or Feedback to Output
Input, I/O, or Feedback to Output Through
Transparent Input Latch
Input Register Setup Time
Input Register Hold Time
Input Latch Setup Time
Input Latch Hold Time
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Product Term Output
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Gate
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
MACH445-15/20 (Com’l)
Disable (Note 2)
1/(t
WICL
+ t
WICH
Gate
D-type
T-type
LOW
HIGH
)
83.3
Min
15
16
14
16
15
15
15
15
10
12
6
6
6
2
2
2
4
2
4
-15
Max
20
22
20
20
15
15
17
19
62.5
Min
20
21
19
21
20
20
20
20
12
16
8
8
8
2
2
5
2
5
2
-20
Max
25
27
25
25
20
20
22
24
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15