D75106CW NEC, D75106CW Datasheet - Page 28

• Manufacturer Part Number: D75106CW
• Description: Search -----> UPD75106CW
• Manufacturer: NEC

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5.8
addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this
buffer is very useful for processing long data in bit units.
Remarks:
5.9
has been generated (see Fig. 8-1).
instruction. However, it cannot be set by the SET1 instruction.
6. INTERRUPT FUNCTIONS
priority assigned.
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
The PD75108 has 7 different interrupt sources and can perform multiplexed interrupt processing with
In addition to that, the PD75108 is also provided with two types of edge detection testable inputs.
The interrupt control circuit of the PD75108 has these functions:
The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal
The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation
Address bit
Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by
using the interrupt enable flag (IExxx) and interrupt master enable flag (IME).
The interrupt start address can be arbitrarily set.
Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS).
Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of
software).
Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
BIT SEQUENTIAL BUFFER .... 16 BITS
L register
POWER-ON FLAG (MASK OPTION)
Symbol
For the pmem.@L addressing, the specification bit is shifted according to the L register.
L = F
3
2
FC3H
BSB3
1
L = C L = B
Fig. 5-7 Bit Sequential Buffer Format
0
3
INCS L
2
FC2H
BSB2
1
L = 8 L = 7
0
3
2
DECS L
FC1H
BSB1
1
PD75104, 75106, 75108
L = 4 L = 3
0
3
2
FC0H
BSB0
1
L = 0
0