TS87C51RD2 ATMEL Corporation, TS87C51RD2 Datasheet - Page 34

• Manufacturer Part Number: TS87C51RD2
• Description: (TS8xC51Rx2) High Performance 8-bit Microcontroller
• Manufacturer: ATMEL Corporation

6.4
6.4.1
Figure 6-10. Framing Error Block Diagram
Figure 6-11. UART Timings in Mode 1
34
TS80C51Rx2 Serial I/O Port
AT/TS8xC51Rx2
Framing Error Detection
SMOD0=X
The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Uni-
versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Serial I/O port includes the following enhancements:
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 6-
10).
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
6-14.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See
11
SMOD0=1
• Framing error detection
• Automatic address recognition
SM0/FE
SMOD1
and
RXD
FE
RI
Figure
SMOD0
SM1
6-12).
Start
bit
SM2
-
D0
REN
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD = 0)
POF
To UART framing error control
D1
TB8
GF1
D2
RB8
GF0
D3
Data byte
D4
PD
TI
D5
IDL
RI
D6
SCON (98h)
PCON (87h)
D7
Stop
bit
4188E–8051–08/06
Figure 6-