TS87C51RD2 ATMEL Corporation, TS87C51RD2 Datasheet
TS87C51RD2
Available stocks
Related parts for TS87C51RD2
TS87C51RD2 Summary of contents
Page 1
... Hardware Watchdog Timer, a more versatile serial channel that facili- www.DataSheet4U.com o C) and Industrial (- High Performance 8-bit Microcontroller TS80C51RA2 TS80C51RD2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 TS87C51RC2 TS87C51RD2 AT80C51RA2 AT80C51RD2 AT83C51RB2 AT83C51RC2 AT83C51RD2 AT87C51RB2 AT87C51RC2 AT87C51RD2 Rev. 4188E–8051–08/06 ...
Page 2
... CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. PDIL40 PLCC44 VQFP44 1.4 TS80C51RA2 TS80C51RD2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 TS87C51RC2 TS87C51RD2 PLCC68 VQFP64 1.4 TS80C51RD2 TS83C51RD2 TS87C51RD2 AT/TS8xC51Rx2 2 ROM (bytes) EPROM (bytes 16k 0 32k 0 64k 0 0 16k ...
Page 3
Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN EA/VPP (3) RD (3) WR 4188E–8051–08/06 (3) (3) ROM RAM /EPROM EUART 256x8 0/16/32/64Kx8 C51 CORE IB-bus CPU Timer 0 INT Parallel I/O Ports & Ext. Bus Ctrl Timer 1 Port 0Port ...
Page 4
SFR Mapping The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3, P4, P5 • Timer registers: ...
Page 5
Table 4-1. Bit Non Bit addressable addressable 0/8 1/9 CH F8h 0000 0000 B F0h 0000 0000 P5 bit CL addressable E8h 0000 0000 1111 1111 ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 PSW D0h 0000 ...
Page 6
Pin Configuration P1 P1.1 / T2EX P1.2 3 P1.3 4 P1.4 5 P1 P1.7 RST 9 P3.0/RxD 10 PDIL/ P3.1/TxD 11 12 P3.2/INT0 CDIL40 P3.3/INT1 13 14 P3.4/T0 15 P3.5/T1 P3.6/WR ...
Page 7
...
Page 8
Pin Number Mnemonic DIL LCC VQFP 1 Vss1 P0.0-P0.7 39-32 43-36 P1.0-P1.7 1-8 2 P2.0-P2.7 ...
Page 9
Pin Number Mnemonic DIL LCC Reset 9 10 ALE/PROG 30 33 PSEN XTAL1 19 21 XTAL2 18 20 5.1 Pin Description for ...
Page 10
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RESET ALE/PROG AT/TS8xC51Rx2 ...
Page 11
PSEN EA/VPP XTAL1 XTAL2 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 4188E–8051–08/06 AT/TS8xC51Rx2 ...
Page 12
TS80C51Rx2 Enhanced Features In comparison to the original 80C52, the TS8xC51Rx2 implements some new features, which are : • The X2 option. • The Dual Data Pointer. • The extended RAM. • The Programmable Counter Array (PCA). • The ...
Page 13
Figure 5-1. Figure 5-2. Mode Switching Waveforms The ...
Page 14
Bit Number Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 fe ature, please refer to ANM072 ava ilable on the web (http://www.atmel.com) AT/TS8xC51Rx2 14 Bit Mnemonic Description Reserved - ...
Page 15
Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the ...
Page 16
Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and ...
Page 17
Expanded RAM (XRAM) The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for increased data parameter handling and high level language usage. RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH ...
Page 18
MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper ...
Page 19
Timer 2 The timer 2 in the 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade controlled by T2CON register (See Table 6-2) and T2MOD register ...
Page 20
Figure 6-2. Auto-reload Mode Up/Down Counter (DCEN = 1) XTAL1 F XTAL 6.2.2 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6-3) . The input clock increments TL2 at frequency F ...
Page 21
It is possible to use timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the RCAP2H and ...
Page 22
Bit Number Reset Value = 0000 0000b Bit addressable Table 6- AT/TS8xC51Rx2 22 Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on ...
Page 23
Bit Number Reset Value = XXXX XX00b Not bit addressable 4188E–8051–08/06 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Reserved - The ...
Page 24
Programmable Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time ...
Page 25
Figure 6-4. PCA Timer/Counter Fosc /12 Fosc / 4 T0 OVF P1.2 Idle Table 6-4. Symbol CIDL WDTE - CPS1 CPS0 ECF 1. 2. The CMOD SFR includes three additional bits associated with the PCA (See Figure 6-4 and Table ...
Page 26
The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the watchdog function on module 4. • The ECF bit which when set causes an interrupt and the PCA ...
Page 27
Figure 6-5. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 ECF PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered, ...
Page 28
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 6-7 shows the CCAPMn settings for the various PCA functions. . Table 6-6. CCAPMn Address Symbol - ECOMn CAPPn ...
Page 29
There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is ...
Page 30
Figure 6-6. PCA Capture Mode ECOMn 6.3.2 16-bit Software Timer/ Compare Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. ...
Page 31
Figure 6-7. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match ...
Page 32
Figure 6-8. PCA High Speed Output Mode Write to Reset CCAPnL Write to CCAPnH 0 Enable 1 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match could happen. Once ...
Page 33
Figure 6-9. 6.3.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or ...
Page 34
TS80C51Rx2 Serial I/O Port The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter ...
Page 35
Figure 6-12. UART Timings in Modes 2 and 3 SMOD0=0 SMOD0=1 SMOD0=1 6.4.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, ...
Page 36
Slave C:SADDR1111 0010b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit communicate with ...
Page 37
Table 6-12. 7 Reset Value = 0000 0000b Not bit addressable Table 6-13. 7 Reset Value = 0000 0000b Not bit addressable Table 6-14. 7 FE/SM0 4188E–8051–08/06 SADEN - Slave Address Mask Register (B9h SADDR - Slave ...
Page 38
Bit Number Reset Value = 0000 0000b Bit addressable Table 6-15. 7 SMOD1 AT/TS8xC51Rx2 38 Bit Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a ...
Page 39
Bit Number Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of ...
Page 40
Interrupt System The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in ...
Page 41
Table 6-16. IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior- ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests ...
Page 42
Table 6-18 Bit Number Reset Value = X000 0000b Bit addressable AT/TS8xC51Rx2 42 IP Register IP - Interrupt Priority Register (B8h PPC PT2 PS Bit Mnemonic Description ...
Page 43
Table 6-19 Bit Number Reset Value = X000 0000b Not bit addressable 4188E–8051–08/06 IPH Register IPH - Interrupt Priority High Register (B7h PPCH PT2H PSH Bit Mnemonic ...
Page 44
Idle Mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the ...
Page 45
Figure 6-14. Power-Down Exit Waveform INT0 INT1 XTAL1 Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter- rupt does no affect the SFRs. Exit from power-down by either reset or external interrupt ...
Page 46
Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is ...
Page 47
Bit Number Reset value XXXX X000 6.8.2 WDT during Power-down and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power- down mode the user does ...
Page 48
TM 6.9 ONCE Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS8xC51Rx2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C51Rx2; the following sequence ...
Page 49
Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by V applied to the device and could be generated for ...
Page 50
Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with exter- nal program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...
Page 51
TS83C51RB2/RC2/RD2 ROM 8.1 ROM Structure The TS83C51RB2/RC2/RD2 ROM memory is divided in three different arrays: • the code array:16/32/64 Kbytes. • the encryption array:64 bytes. • the signature array:4 bytes. 8.2 ROM Lock System The program Lock system, when ...
Page 52
Verify Algorithm Refer to Section “Verify algorithm”. AT/TS8xC51Rx2 52 4188E–8051–08/06 ...
Page 53
TS87C51RB2/RC2/RD2 EPROM 9.1 EPROM Structure The TS87C51RB2/RC2/RD2 EPROM is divided in two different arrays: • the code array:16/32/64 Kbytes. • the encryption array:64 bytes. In addition a third non programmable array is implemented: • the signature array: 4 bytes. ...
Page 54
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. 9.2.3 Signature bytes The TS87C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in Section “Signature bytes”. 9.3 EPROM ...
Page 55
Figure 9- ...
Page 56
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. Figure 9-2. Programming and Verification Signal’s Waveform ...
Page 57
... FCh 60h 37h 60h B7h 60h 3Bh 60h BBh 61h FFh AT/TS8xC51Rx2 Product name: TS87C51RD2 Product name: TS83C51RC2 Product name: TS87C51RC2 Product name: TS83C51RB2 Product name: TS87C51RB2 Product revision number 57 ...
Page 58
Electrical Characteristics 11.1 Absolute Maximum Ratings Ambiant Temperature Under Bias commercial......................................................0°C to 70° industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage ........................................-0 ...
Page 59
Table 11-1. DC Parameters in Standard Voltage Symbol Parameter V Output High Voltage, ports Output High Voltage, port 0 OH1 V Output High Voltage,ALE, PSEN OH2 R RST Pulldown Resistor RST I Logical ...
Page 60
... Logical Transition Current, ports RST Pulldown Resistor RST CIO Capacitance of I/O Buffer I Power-down Current PD Power-down Current (Only for TS87C51RD2 I PD S287-xxx Very Low power Power Supply Current Maximum values, X1 under (7) mode: RESET I Power Supply Current Maximum values, X1 ...
Page 61
Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these ...
Page 62
Figure 11-3. I Figure 11- ...
Page 63
+70°C (commercial temperature range -40°C to +85°C (industrial temperature range Table 11-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN ...
Page 64
External Program Memory Characteristics Table 11-5. Symbol T T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T PXAV T AVIV T PLAZ Table 11-6. Speed Symbol T T LHLL ...
Page 65
Table 11-7. Symbol 11.5.3 External Program Memory Read Cycle Figure 11-6. External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 4188E–8051–08/06 AC Parameters for a Variable ...
Page 66
External Data Memory Characteristics Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T RLAZ T WHLH Table 11-8. Speed -M 40 MHz ...
Page 67
Table 11-9. Symbol 11.5.5 External Data Memory Write Cycle Figure 11-7. External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 ...
Page 68
Figure 11-8. External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 11.5.7 Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 11-10. AC Parameters ...
Page 69
Table 11-11. AC Parameters for a Variable Clock: derating formula Symbol 11.5.8 Shift Register Timing Waveforms Figure 11-9. Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA ...
Page 70
EPROM Programming and Verification Characteristics T = 21°C to 27° Symbol 1/T T AVGL T GHAX T DVGL T GHDX T EHSH T SHGL T GHSL T GLGH T AVQV T ELQV T EHQZ ...
Page 71
External Clock Drive Characteristics (XTAL1) Symbol Parameter T Oscillator Period CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL T /T Cyclic ratio in X2 mode CHCX CLCX 11.5.12 External Clock ...
Page 72
Clock Waveforms Valid in normal clock mode mode XTAL2 signal must be changed to XTAL2 divided by two. Figure 11-14. Clock Waveforms STATE4 CLOCK P1P2 XTAL2 ALE E X ...
Page 73
Ordering Information Part Number Memory size TS80C51RA2-MCA Romless TS80C51RA2-MCB Romless TS80C51RA2-MCE Romless TS80C51RA2-MIA Romless TS80C51RA2-MIB Romless TS80C51RA2-MIE Romless TS80C51RA2-LCA Romless TS80C51RA2-LCB Romless TS80C51RA2-LCE Romless TS80C51RA2-LIA Romless TS80C51RA2-LIB Romless TS80C51RA2-LIE Romless TS80C51RA2-VCA Romless TS80C51RA2-VCB Romless TS80C51RA2-VCE Romless TS80C51RA2-VIA Romless TS80C51RA2-VIB ...
Page 74
Part Number Memory size AT80C51RA2-RLTCV Romless AT80C51RA2-3CSIV Romless AT80C51RA2-SLSIV Romless AT80C51RA2-RLSIV Romless TS80C51RD2-MCA Romless TS80C51RD2-MCB Romless TS80C51RD2-MCE Romless TS80C51RD2-MIA Romless TS80C51RD2-MIB Romless TS80C51RD2-MIE Romless TS80C51RD2-LCA Romless TS80C51RD2-LCB Romless TS80C51RD2-LCE Romless TS80C51RD2-LIA Romless TS80C51RD2-LIB Romless TS80C51RD2-LIE Romless TS80C51RD2-VCA Romless TS80C51RD2-VCB Romless ...
Page 75
Part Number Memory size TS87C51RB2-MIB OTP 16k Bytes TS87C51RB2-MIE OTP 16k Bytes TS87C51RB2-LCA OTP 16k Bytes TS87C51RB2-LCB OTP 16k Bytes TS87C51RB2-LCE OTP 16k Bytes TS87C51RB2-LIA OTP 16k Bytes TS87C51RB2-LIB OTP 16k Bytes TS87C51RB2-LIE OTP 16k Bytes TS87C51RB2-VCA OTP 16k Bytes ...
Page 76
... TS87C51RD2-LCE OTP 64k Bytes TS87C51RD2-LIA OTP 64k Bytes TS87C51RD2-LIB OTP 64k Bytes TS87C51RD2-LIE OTP 64k Bytes TS87C51RD2-VCA OTP 64k Bytes TS87C51RD2-VCB OTP 64k Bytes TS87C51RD2-VCE OTP 64k Bytes TS87C51RD2-VCL OTP 64k Bytes TS87C51RD2-VIA OTP 64k Bytes TS87C51RD2-VIB OTP 64k Bytes TS87C51RD2-VIE ...
Page 77
Part Number Memory size AT87C51RD2-RLTUM OTP 64k Bytes AT87C51RD2-3CSUL OTP 64k Bytes AT87C51RD2-SLSUL OTP 64k Bytes AT87C51RD2-RLTUL OTP 64k Bytes TS83C51RB2-MCA ROM 64k Bytes TS83C51RB2-MCB ROM 16k Bytes TS83C51RB2-MCE ROM 16k Bytes TS83C51RB2-MIA ROM 16k Bytes TS83C51RB2-MIB ROM 16k Bytes ...
Page 78
Part Number Memory size TS83C51RC2-MIB ROM 32k Bytes TS83C51RC2-MIE ROM 32k Bytes TS83C51RC2-LCA ROM 32k Bytes TS83C51RC2-LCB ROM 32k Bytes TS83C51RC2-LCE ROM 32k Bytes TS83C51RC2-LIA ROM 32k Bytes TS83C51RC2-LIB ROM 32k Bytes TS83C51RC2-LIE ROM 32k Bytes TS83C51RC2-VCA ROM 32k Bytes ...
Page 79
Part Number Memory size TS83C51RD2-VCE ROM 64k Bytes TS83C51RD2-VIA ROM 64k Bytes TS83C51RD2-VIB ROM 64k Bytes TS83C51RD2-VIE ROM 64k Bytes AT83C51RD2-3CSUM ROM 64k Bytes AT83C51RD2-SLSUM ROM 64k Bytes AT83C51RD2-RLTUM ROM 64k Bytes AT83C51RD2-3CSUL ROM 64k Bytes AT83C51RD2-SLSUL ROM 64k Bytes ...
Page 80
Package Drawings 14.1 PLCC44 AT/TS8xC51Rx2 80 4188E–8051–08/06 ...
Page 81
PDIL40 4188E–8051–08/06 AT/TS8xC51Rx2 81 ...
Page 82
VQFP44 AT/TS8xC51Rx2 82 4188E–8051–08/06 ...
Page 83
VQFP64 4188E–8051–08/06 AT/TS8xC51Rx2 83 ...
Page 84
PLCC68 AT/TS8xC51Rx2 84 4188E–8051–08/06 ...
Page 85
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. © Atmel Corporation 2006. All rights reserved. Atmel are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...