ISL12028 Intersil Corporation, ISL12028 Datasheet - Page 17

• Manufacturer Part Number: ISL12028
• Manufacturer: Intersil Corporation

Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the V
voltage (V
below V
V
V
Power up and power down waveforms are shown in
Figure 4. The LVR circuit is to be designed so the RESET
signal is valid down to V
When the LVR signal is active, unless the part has been
switched into the battery mode, the completion of an in-
progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
operations. See “I
Backup and LVR Operation”.
Serial Communication
The device supports the I
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. (See Figure 16.)
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 17.
DD
RESET
line rises above V
, then the RESET output will remain asserted low.
RESET
RESET
. The reset pulse will timeout 250ms after the
), then generates a RESET pulse if it is
2
C Communications During Battery
RESET
DD
SDA
2
SCL
C bidirectional serial bus protocol.
SDA
SCL
DD
= 1.0V.
17
. If the V
line versus a preset threshold
DD
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
FIGURE 17. VALID START AND STOP CONDITIONS
remains below
DATA STABLE
START
ISL12028
DATA CHANGE
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 17.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits of
data. Refer to Figure 18.
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
eight bit word. The device will not acknowledge if the slave
address byte is incorrect.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.
DATA STABLE
STOP
April 17, 2006
FN8233.3