ISL12028 Intersil Corporation, ISL12028 Datasheet - Page 16

• Manufacturer Part Number: ISL12028
• Manufacturer: Intersil Corporation

These two power control situations are illustrated in Figures
13 and 14.
OPTION 2 - LEGACY POWER CONTROL MODE
(DEFAULT)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from V
comparing the voltages and the device operates from
whichever is the higher voltage.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1”
• Normal Mode (V
To transition from the V
conditions must be met:
V
• Battery Backup Mode (V
The device will switch from the V
following condition occurs:
V
The Legacy Mode power control conditions are illustrated in
Figure 15.
DD
DD
FIGURE 13. BATTERY SWITCHOVER WHEN V
FIGURE 14. BATTERY SWITCHOVER WHEN V
V
V
V
V
V
V
< V
> V
TRIP
TRIP
DD
BAT
BAT
DD
V
BAT
BAT
BAT
- V
+V
- V
V
BATHYS
TRIP
BATHYS
BATHYS
DD
) to Battery Backup Mode (V
BATTERY BACKUP
DD
BATTERY BACKUP
to V
BAT
MODE
16
DD
MODE
) to Normal Mode (V
BAT
BAT
to V
mode, the following
BAT
to V
is simply done by
DD
V
TRIP
V
mode when the
BAT
+ V
BAT
BAT
+ V
TRIPHYS
BAT
< V
> V
DD
BATHYS
3.0V
2.2V
2.2V
1.8V
)
)
TRIP
TRIP
ISL12028
Power On Reset
Application of power to the ISL12028 activates a Power On
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
When V
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
Watchdog Timer Operation
The watchdog timer timeout period is selectable. By writing a
value to WD1 and WD0, the watchdog timer can be set to 3
different time out periods or off. When the Watchdog timer is
set to off, the watchdog circuit is configured for low power
operation. See Table 7.
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode. See Figure 3.
- It prevents the system microprocessor from starting to
- It prevents the processor from operating prior to
- It allows time for an FPGA to download its configuration
- It prevents communication to the EEPROM, greatly
V
BAT
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
operate with insufficient voltage.
stabilization of the oscillator.
prior to initialization of the circuit.
reducing the likelihood of data corruption on power up.
WD1
1
1
0
0
DD
exceeds the device V
Off
WD0
1
0
1
0
V
DD
TABLE 7.
RESET
VOLTAGE
DURATION
threshold value for
disabled
250ms
750ms
1.75s
On
April 17, 2006
FN8233.3
In