EMC2102 Standard Microsystems Corporation, EMC2102 Datasheet - Page 38

• Manufacturer Part Number: EMC2102
• Description: Rpm-based Fan Controller with HW Thermal Shutdown
• Manufacturer: Standard Microsystems Corporation

Revision 1.95 (10-19-06)
6.9
30h
31h
ADDRESS
Bit 2 - EXT3_MASK - masks the ERR3 and TRD3 bits from asserting the ALERT# pin.
Bit 1 - EXT2_MASK - masks the ERR2 and TRD2 bits from asserting the ALERT# pin.
Bit 0 - EXT1_MASK - masks the ERR1 and TRD1 bits from asserting the ALERT# pin.
The Beta Configuration Registers control advanced temperature measurement features for each
External Diode channel. The Beta Configuration Registers are software locked.
When the External Diode 1 Channel is selected by the SHDN_SEL pin to be the hardware shutdown
input channel (see
Writing to the register will have no affect and reading from it will always reflect the current beta settings
(05h).
For the External Diode 3 Channel, the beta compensation setting is fixed at ‘111b’ indicating that the
beta compensation is disabled.
Bit 2 - 0 - BETAx[2:0] - hold a value that corresponds to a range of betas that the Beta Compensation
circuitry can compensate for. The Beta Configuration Registers activate the Beta Compensation
circuitry if any value besides 111 is written. The register should be set with a value corresponding to
the lowest expected value of beta for the PNP transistor being used as a temperature sensing device.
See
CPU’s the optimal beta setting is 04h.
Beta Configuration Registers
External Diode 1
Beta
Configuration
External Diode 2
Beta
Configuration
‘0’ (default) - the FAN_STALL bit will assert the ALERT# pin if set in the Interrupt Status Register 2.
‘1’ - the FAN_STALL bit will not assert the ALERT# pin though will still update the Interrupt Status
Register 2 normally.
‘0’ (default) - the ERR3 and TRD3 bits will assert the ALERT# pin if they are set in the Interrupt
Status Register 1.
‘1’ - the ERR3 and TRD3 bits will not assert the ALERT# pin though they will still update the
Interrupt Status Register 1 normally.
‘0’ (default) - the ERR2 and TRD2 bits will assert the ALERT# pin if they are set in the Interrupt
Status Register 1.
‘1’ - the ERR2 and TRD2 bits will not assert the ALERT# pin though they will still update the
Interrupt Status Register 1 normally.
‘0’ (default) - the ERR1 and TRD1 bits will assert the ALERT# pin if they are set in the Interrupt
Status Register 1.
‘1’ - the ERR1 and TRD1 bits will not assert the ALERT# pin though they will still update the
Interrupt Status Register 1 normally.
Table 6.13
REGISTER
for supported beta ranges. The default setting is calibrated for 65nm CPU’s. For 90nm
Table
Table 6.12 Beta Configuration Registers
-
-
B7
5.4), the External Diode 1 Beta Configuration Register becomes read only.
-
-
B6
DATASHEET
-
-
B5
38
-
-
B4
-
-
RPM-Based Fan Controller with HW Thermal Shutdown
B3
BETA1[2:0]
BETA2[2:0]
B2
B1
B0
03h
03h
DEFAULT
SMSC EMC2102
Datasheet