ADC08351CIMTC National Semiconductor, ADC08351CIMTC Datasheet - Page 14

• Manufacturer Part Number: ADC08351CIMTC
• Description: 8-Bit/ 42 MSPS/ 40 mW A/D Converter
• Manufacturer: National Semiconductor

www.national.com
Applications Information
inject noise into the system and may be difficult to detect with
an oscilloscope. A resistor of about 50
with the offending digital input will usually eliminate the prob-
lem.
Care should be taken not to overdrive the inputs of the
ADC08351 (or any device) with a device that is powered
from supplies outside the range of the ADC08351 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers have to charge for
each conversion, the more instantaneous digital current is
required from V
spikes can couple into the analog section, degrading dy-
namic performance. While adequate bypassing and main-
taining separate analog and digital ground planes will reduce
this problem on the board, this coupling can still occur on the
ADC08351 die. Buffering the digital data outputs (with a
74ACQ541, for example) may be necessary if the data bus
to be driven is heavily loaded.
Dynamic performance can also be improved by adding se-
ries resistors at each digital output, reducing the energy
coupled back into the converter output pins by limiting the
output slew rate. A reasonable value for these resistors is
about 47 .
D
and DGND. These large charging current
to 100
(Continued)
in series
14
Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the in-
put alternates between 4 pF and 11 pF with the clock. This
dynamic capacitance is more difficult to drive than a fixed ca-
pacitance, so care should be taken in choosing a driving de-
vice. The CLC409, CLC440, LM6152, LM6154, LM6181 and
LM6182 are good devices for driving the ADC08351. Also,
an amplifier with insufficient gain-bandwidth may limit the
overall frequency response of the overall circuit.
Using an operational amplifier in an insufficient gain
configuration to drive the analog input. Operational am-
plifiers, while some may be unity gain stable, generally ex-
hibit more distortion at low in-circuit gains than at higher
gains.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance. Simple gates with RC timing
is generally inadequate.
Not considering the timing relationships, especially t
Timing is always important and gets more critical with higher
speeds. If the output data is latched or looked at when that
data is in transition, you may see excessive noise and distor-
tion of the output signal.
OD
.