MAX7000AFamily Altera Corporation, MAX7000AFamily Datasheet - Page 48

• Manufacturer Part Number: MAX7000AFamily
• Description: Max 7000a Programmable Logic Device Family
• Manufacturer: Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet
48
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
Symbol
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 26. EPM7256A External Timing Parameters
Input to non-registered
output
I/O input to non-
registered output
Global clock setup time
Global clock hold time
Global clock setup time
of fast input
Global clock hold time of
fast input
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output
delay
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock
period
Maximum internal array
clock frequency
Parameter
C1 = 35 pF
(2)
C1 = 35 pF
(2)
(2)
(2)
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(3)
(2)
(2),
(2)
(2),
Conditions
(4)
(4)
156.3
156.3
Min
3.7
0.0
2.5
0.0
1.0
3.0
3.0
0.8
1.9
1.0
3.0
3.0
3.0
-6
Max
6.0
6.0
3.3
6.2
6.4
6.4
Note (1)
125.0
125.0
Min
4.6
0.0
3.0
0.0
1.0
3.0
3.0
1.0
2.7
1.0
3.0
3.0
3.0
-7
Speed Grade
Max
7.5
7.5
4.2
7.8
8.0
8.0
93.5
93.5
Min
6.2
0.0
4.0
4.0
1.4
4.0
4.0
4.0
4.0
3.0
0.0
1.0
1.0
-10
Max
10.0
10.0
10.3
10.7
10.7
5.5
Altera Corporation
78.1
78.1
Min
7.4
0.0
3.0
0.0
1.0
4.0
4.0
1.6
5.1
1.0
4.0
4.0
4.0
-12
12.0
12.0
12.4
12.8
12.8
Max
6.6
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns