MAX7000AFamily Altera Corporation, MAX7000AFamily Datasheet - Page 17

• Manufacturer Part Number: MAX7000AFamily
• Description: Max 7000a Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Programming
with External
Hardware
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
f
f
f
For more information on using the Jam STAPL language, see
Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor)
and
Processor).
ISP circuitry in MAX 7000AE devices is compliant with the IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
MAX 7000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the MPU, and the appropriate device
adapter. The MPU performs continuity checks to ensure adequate
electrical contact between the adapter and the device.
For more information, see the
The Altera software can use text- or waveform-format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices.
For more information, see
MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1.
devices. The pin-out tables, available from the Altera web site
(http://www.altera.com), show the location of the JTAG control pins for
each device. If the JTAG interface is not required, the JTAG pins are
available as user I/O pins.
Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded
Table 5
describes the JTAG instructions supported by MAX 7000A
MAX 7000A Programmable Logic Device Data Sheet
Programming Hardware
Altera Programming Hardware Data Sheet.
Manufacturers.
Application
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