STPMC1 ST Microelectronics, STPMC1 Datasheet - Page 44

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STPMC1

Manufacturer Part Number
STPMC1
Description
Programmable poly-phase energy calculator IC
Manufacturer
ST Microelectronics
Datasheet

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Theory of operation
9.17.1
Figure 13. Group 0 data records
44/76
DRP
DRP
DRP
DRP
DAP
DAP
DAP
DAP
PRD
PRD
PRD
PRD
DFP
DFP
DFP
DFP
Group 0 data records
0.1 DAP:
0.2 DRP:
0.3 DFP:
0.4 PRD:
Equation 10
parity
parity
parity
parity
parity
parity
parity
parity
parity
parity
parity
parity
parity
parity
parity
parity
4 bit
4 bit
4 bit
4 bit
4 bit
4 bit
3- phase active energy wide band: 20-bit accumulator of 3-ph active energy wide band
(see paragraph
3-ph lower status: bits [0:7] of 3-phase status (see
3- phase reactive energy: 20-bit accumulator of 3-ph reactive energy (see paragraph
9.11
3-ph up status: bits [8:11] of 3-phase status (see
TSG bits: 4 TSG mode signal (see paragraph
3-phase active energy fundamental: 20-bit accumulator of 3-ph active energy from
fundamental harmonic (see paragraph
system signals: commands BANK-PUMP-TST0-TST1-TST2-RD-WE-precharge (see
paragraph
period: 12-bit line period measurement (see paragraph
from R-phase signal, if it is missing from S-phase then from T-phase. The value of the
period can be calculated from the decimal value of period as:
DC uN: 16-bit DC component of voltage channel of NDSP. It may be DAN-V or DAH
according to the value of ENH bit. For example it is DC offset in sigma delta uN if
ENH=0, or DC value of magnetic field if ENH is set and a magnetic sensor is connected
via STPMSx on DAH input.
)
9.20
)
9.11
period
period
period
period
3-phase active energy fundamental
3-phase active energy fundamental
3-phase active energy fundamental
3-phase active energy fundamental
12 bit
12 bit
12 bit
12 bit
3-phase active energy wide band
3-phase active energy wide band
3-phase active energy wide band
3-phase active energy wide band
)
3-phase reactive energy
3-phase reactive energy
3-phase reactive energy
3-phase reactive energy
Doc ID 15728 Rev 1
20 bit
20 bit
20 bit
20 bit
T
period
9.11
f
MCLK
)
2
9.20
6
Table 29
)
Table 29
9.6
DC uN
DC uN
DC uN
DC uN
)
16 bit
16 bit
16 bit
16 bit
). By default it is calculated
)
3-ph up status
3-ph up status
3-ph up status
3-ph up status
4 bit
4 bit
4 bit
4 bit
3-ph lower status
3-ph lower status
3-ph lower status
3-ph lower status
system signals
system signals
system signals
system signals
8 bit
8 bit
8 bit
8 bit
TSG bits
TSG bits
TSG bits
TSG bits
4 bit
4 bit
4 bit
4 bit
STPMC1

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