STPMC1 ST Microelectronics, STPMC1 Datasheet - Page 23

• Manufacturer Part Number: STPMC1
• Description: Programmable poly-phase energy calculator IC
• Manufacturer: ST Microelectronics

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STPMC1
Table 10.
Table 11.
9.5
4.194 MHz
4.915 MHz
8.192 MHz
9.830 MHz
f
XTAL1
4.194 MHz
4.915 MHz
8.192 MHz
9.830 MHz
The clock generator is responsible for two tasks.
The first is to retard the turn-on of some functional blocks after POR in order to help a
smooth start of external power supply circuitry by keeping off all major loads. For this
reason, all blocks of the digital part, except the SPI interface, are held in a reset state for 125
ms after a power on reset (see
The second task of the clock generator is to provide all necessary clocks for the digital part.
In this task, a MDIV and FR1 programming bits are used to inform the device about the
nominal frequency value from XTAL1 (f
Four nominal frequencies are possible through proper setting of the MDIV and FR1 bits (see
Table
The internal master clock f
Frequency settings through MDIV and FR1
Through the HSA bit the frequency of the output pin CLK (f
the STPMSx devices, can be derived as reported in
CLK pin frequency settings through HSA
Zero crossing detection (signal ZCR)
The STPMC1 has a zero crossing detection circuit on the voltage channel that can be used
to synchronize some utility equipment to zero crossing or max of line voltage events. This
circuit produces the internal signal ZCR that has a falling edge every zero crossing of one of
the line voltages and a rising edge every peak (positive or negative) of one of the line
voltages.
The ZCR signal is a 3-phase voltage zero cross signal. It is the result of a XNOR of the ZCR
of each phase. The ZCR of each of the three-phases is a 100 Hz signal, so a 3-phase ZCR
is 300 Hz signal. The ZCR signal is available on the MOP pin only when the STPMC1 works
as a peripheral with the configuration bit APL=0.
f
XTAL1
10).
MDIV (1 bit)
0
0
1
1
MCLK
Doc ID 15728 Rev 1
Section
is derived from f
HSA (1 bit)
0
1
0
1
0
1
0
1
XTAL1
9.3).
).
FR1 (1 bit)
XTAL1
0
1
0
1
Table
as shown in
CLK
11.
), which provides the clock for
Table
1.049 MHz
2.097 MHz
1.229 MHz
2.458 MHz
2.048 MHz
4.096 MHz
2.458 MHz
4.915 MHz
Theory of operation
f
10.
CLK
8.389 MHz
9.830 MHz
8.192 MHz
9.830 MHz
f
MCLK
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