MBM29PL160TD-90PF Meet Spansion Inc., MBM29PL160TD-90PF Datasheet - Page 26

• Manufacturer Part Number: MBM29PL160TD-90PF
• Description: Page Mode Flash Memory Cmos 16m 2m ? 8/1m ? 16 Bit
• Manufacturer: Meet Spansion Inc.

26
MBM29PL160TD/BD
*1: Performing successive read operations from any address will cause DQ
*2: Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
Data Protection
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-up Write Inhibit
Sector Protection
Program
Erase
Erase Suspend Read
(Erase Suspended Sector) *
Erase-Suspend Program
at the DQ
The MBM29PL160TD/BD is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 2.3 V (typically 2.4 V). If V
are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Writing is inhibited by holding any one of OE = V
be a logical zero while OE is a logical one.
Power-up of the devices with WE = CE = V
The internal state machine is automatically reset to read mode on power-up.
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressed to protected sectors.
Any commands to program or erase addressed to protected sector are ignored (see “Sector Protection” in
■FUNCTIONAL DESCRIPTION).
CC
CC
Write Inhibit
level is greater than V
2
bit. However, successive reads from the erase-suspended sector will cause DQ
Mode
1
LKO
CC
. It is the users responsibility to ensure that the control pins are logically correct
< V
LKO
Retired Product DS05-20872-4E_July 31, 2007
, the command register is disabled and all internal program/erase circuits
CC
is above 2.3 V.
Toggle Bit Status Table
-75/90
CC
IL
DQ
DQ
DQ
and OE = V
power-up and power-down, a write cycle is locked out for V
0
1
7
7
7
IL
, CE = V
IH
will not accept commands on the rising edge of WE.
IH
, or WE = V
Toggle *
Toggle
Toggle
DQ
1
IH
6
. To initiate a write, CE and WE must
6
to toggle.
1
2
to toggle.
Toggle
Toggle
DQ
1 *
1
CC
2
2
power-up
CC
less